MEMS and CMOS integration with low-temperature bonding

Patent metadata

Field	Value
Publication number	US-9394161-B2
Application number	US-201514639492-A
Country	US
Kind code	B2
Filing date	Mar 5, 2015
Priority date	Nov 14, 2014
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

The present disclosure relates to method of forming a MEMS device that mitigates the above mentioned difficulties. In some embodiments, the present disclosure relates to a method of forming a MEMS device, which forms one or more cavities within a first side of a carrier substrate. The first side of the carrier substrate is then bonded to a dielectric layer disposed on a micro-electromechanical system (MEMS) substrate, and the MEMS substrate is subsequently patterned to define a soft mechanical structure over the one or more cavities. The dielectric layer is then selectively removed, using a dry etching process, to release the one or more soft mechanical structures. A CMOS substrate is bonded to a second side of the MEMS substrate, by way of a bonding structure disposed between the CMOS substrate and the MEMS substrate, using a low-temperature bonding process.

First claim

What is claimed is:

1. A method of forming an integrated chip, comprising:
forming one or more cavities within a first side of a carrier substrate;
bonding the first side of the carrier substrate to a dielectric layer disposed on a micro-electromechanical system (MEMS) substrate;
selectively patterning the MEMS substrate to define one or more soft mechanical structures over the one or more cavities;
selectively removing the dielectric layer using a dry etching process to release the one or more soft mechanical structures; and
bonding a CMOS substrate to a second side of the MEMS substrate by way of a bonding structure disposed between the CMOS substrate and the MEMS substrate.

2. The method of claim 1 , further comprising:
forming a plurality of openings in a dielectric material over the CMOS substrate, wherein the plurality of openings expose an upper metal interconnect layer within a back-end-of-the-line (BEOL) metal stack;
forming a first bonding layer on the upper metal interconnect layer; and
bringing the first bonding layer into contact with a second bonding layer.

3. The method of claim 1 , wherein bonding the CMOS substrate to a second side of the MEMS substrate is performed at a temperature of less than approximately 400° C.

4. The method of claim 1 , wherein the bonding structure comprises an intermetallic compound having a melting temperature of greater than approximately 300° C.

5. The method of claim 4 , wherein the intermetallic compound comprises one or more of a copper (Cu), gold (Au), tin (Sn), or indium (In).

6. The method of claim 1 , wherein the dry etching process comprises an etchant including a vaporized hydroflouric acid.

7. The method of claim 6 , wherein the dry etching process causes the dielectric layer to be set back from sidewalls of the MEMS substrate and the carrier substrate.

8. The method of claim 7 , wherein the dielectric layer has a cross-sectional profile that has ratio of variation in width to height that is in a range of between approximately 0.01 and approximately 4.

9. The method of claim 1 , further comprising:
forming one or more anti-stiction bumps within the one or more cavities, during formation of the one or more cavities.

10. A method of forming an integrated chip, comprising:
selectively etching a first side of a carrier substrate to form one or more cavities;
bonding the first side of the carrier substrate to a dielectric layer disposed on a micro-electromechanical system (MEMS) substrate;
forming one or more bonding layers on the MEMS substrate;
selectively patterning the MEMS substrate to define one or more soft mechanical structures over the one or more cavities;
selectively etching the dielectric layer by a dry etching process to release the one or more soft mechanical structures; and
bonding a CMOS substrate to a second side of the MEMS substrate at a temperature of less than approximately 400° C., wherein bonding the CMOS substrate to the MEMS substrate causes the one or more bonding layers to form a bonding structure comprising an intermetallic compound disposed between the CMOS substrate and the MEMS substrate.

11. The method of claim 10 , further comprising:
forming a plurality of openings in a dielectric material over the CMOS substrate, wherein the plurality of openings expose an upper metal interconnect layer within a back-end-of-the-line (BEOL) metal stack;
forming a first bonding layer on the upper metal interconnect layer; and
forming one or more additional bonding layers over the first bonding layer.

12. The method of claim 10 , wherein the dielectric layer has a cross-sectional profile that has ratio of variation in width to height that is in a range of between approximately 0.01 and approximately 4.

13. The method of claim 10 , wherein the bonding structure comprises an intermetallic compound has a melting temperature of greater than approximately 300° C.

14. The method of claim 10 , wherein the intermetallic compound comprises one or more of a copper (Cu), gold (Au), tin (Sn), or indium (In).

15. The method of claim 10 , wherein the dry etching process comprises an etchant comprising vaporized hydroflouric acid.

16. A method of forming an integrated chip, comprising:
forming a cavity within a first side of a carrier substrate;
bonding the first side of the carrier substrate to a dielectric layer disposed on a micro-electromechanical system (MEMS) substrate;
selectively patterning the MEMS substrate to form one or more openings extending through the MEMs substrate to contact the dielectric layer at a location above the cavity;
selectively etching the dielectric layer between the MEMs substrate and the cavity using an etchant that contacts the dielectric layer through the openings; and
bonding a CMOS substrate to a second side of the MEMS substrate by way of a bonding structure disposed between the CMOS substrate and the MEMS substrate.

17. The method of claim 16 , wherein etching the dielectric layer results in a sidewall of the dielectric layer, which faces the cavity and that varies laterally as a vertical position between the CMOS substrate and the MEMs substrate changes.

18. The method of claim 16 , wherein the dielectric layer has a sidewall facing the cavity, which is set back from a sidewall of the cavity.

19. The method of claim 16 , wherein selectively patterning the MEMs substrate forms one or more additional openings extending through the MEMs substrate at a location that is laterally offset from the cavity.

20. The method of claim 16 , wherein the CMOS substrate is bonded to the second side of the MEMs substrate at a temperature of less than approximately 400° C.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Chun-Wen
• Chu Chia-Hua
• Peng Jung-Huei

Classifications

• B81C1/00238 Primary

  Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure · CPC title

• B81B2201/0235

  Accelerometers · CPC title

• B81C2203/035

  Soldering · CPC title

• B81C2203/0792

  Forming interconnections between the electronic processing unit and the micromechanical structure · CPC title

• B81C3/00

  Assembling of devices or systems from individually processed components · CPC title