Package structure with embedded core

Patent metadata

Field	Value
Publication number	US-10937726-B1
Application number	US-202016746681-A
Country	US
Kind code	B1
Filing date	Jan 17, 2020
Priority date	Nov 27, 2019
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

First claim

What is claimed is:

1. A semiconductor device assembly, comprising:
a silicon core structure having a first side opposing a second side, the silicon core structure having a thickness less than 1000 μm, the silicon core structure further comprising:
a via comprising a via surface that defines an opening extending through the silicon core structure from the first side to the second side;
an oxide layer formed over the first side, the second side, and the via surface; and
a conductive interconnection formed through the via and protruding from the first side and the second side;

an insulating layer disposed over the oxide layer on the first side, the second side, and within the opening;
a first redistribution layer formed on the first side; and
a second redistribution layer formed on the second side, wherein the first redistribution layer and the second redistribution layer each have one or more conductive contacts formed thereon.

2. The semiconductor device assembly of claim 1 , wherein the oxide layer comprises a thermal oxide.

3. The semiconductor device assembly of claim 1 ,
wherein the insulating layer comprises an epoxy resin.

4. The semiconductor device assembly of claim 3 , wherein the epoxy resin comprises silica particles.

5. The semiconductor device assembly of claim 4 , wherein the silica particles in the insulating layer range in size between about 300 nm and about 600 nm.

6. The semiconductor device assembly of claim 3 , wherein the insulating layer has a thickness of between about 5 μm and about 50 μm.

7. The semiconductor device assembly of claim 3 , wherein the first redistribution layer and the second redistribution layer each further comprise:
an adhesion layer formed on the insulating layer, the adhesion layer comprising molybdenum;
a seed layer formed on the adhesion layer; and
a copper layer formed over the seed layer.

8. The semiconductor device assembly of claim 7 , wherein the adhesion layer has a thickness between about 10 nm and about 500 nm.

9. The semiconductor device assembly of claim 1 , wherein the conductive interconnection within the opening is circumferentially defined by the insulating layer, and the insulating layer within the opening is circumferentially defined by the oxide layer.

10. The semiconductor device assembly of claim 1 , wherein the silicon core structure comprises a polycrystalline p-type or n-type silicon substrate.

11. The semiconductor device assembly of claim 1 , wherein the conductive interconnection comprises a hollow core.

12. A semiconductor device assembly, comprising:
a silicon core structure having a first surface opposing a second surface, the silicon core structure having a thickness less than 1000 μm, the silicon core structure further comprising:
a via comprising a via surface that defines an opening extending through the silicon core structure from the first surface to the second surface; and
a passivating layer surrounding the silicon core structure, the passivating layer comprising a thermal oxide; and

a dielectric layer formed over the passivating layer on at least the first surface, the second surface, and within the opening, the dielectric layer comprising an epoxy resin having silica particles disposed therein.

13. The semiconductor device assembly of claim 12 , wherein the silicon core structure comprises a crystalline silicon substrate.

14. The semiconductor device assembly of claim 12 ,
wherein the via has a diameter less than about 500 μm.

15. The semiconductor device assembly of claim 14 , wherein the via is one of a plurality of vias disposed through the silicon core structure, a pitch between each via of the plurality of vias has a distance between about 40 μm and 1000 μm.

16. The semiconductor device assembly of claim 12 , further comprising a first redistribution layer formed on the dielectric layer.

17. The semiconductor device assembly of claim 16 , wherein the first redistribution layer further comprises:
an adhesion layer formed on the dielectric layer, the adhesion layer comprising molybdenum;
a seed layer formed on the adhesion layer; and
a copper layer formed over the seed layer.

18. The semiconductor device assembly of claim 12 , further comprising a conductive interconnection formed within the opening extending from the first side to the second side, the conductive interconnection circumferentially defined by the dielectric layer.

19. A semiconductor device assembly, comprising:
a silicon core structure having a first side opposing a second side and a plurality of vias that extend from the first side to the opposing second side, each of the plurality of vias comprising a via surface that defines an opening extending through the core silicon structure from the first side to the second side;
a passivating layer disposed over the first side, the second side and the via surface of each of the plurality of vias of the silicon core structure, the passivating layer comprising a thermal oxide;
a dielectric layer disposed over the passivating layer on the first side and the second side, and within the opening of each of the plurality of vias, the dielectric layer comprising an epoxy resin; and
a redistribution layer formed on the dielectric layer, the redistribution layer comprising:
an adhesion layer formed on the dielectric layer, the adhesion layer comprising molybdenum;
a copper seed layer formed on the adhesion layer; and
a copper layer formed on the copper seed layer.

20. The semiconductor device assembly of claim 19 , wherein
the dielectric layer further comprises a through assembly via that extends through the dielectric layer disposed within the opening of each of the plurality of vias,
each of the through assembly vias extend through the dielectric layer from the first side to the second side of the silicon core structure, and
each of the through assembly vias has a conductive interconnection formed therein.

Assignees

• Applied Materials Inc

Inventors

• Chen Han-Wen
• Verhaverbeke Steven
• Park Giback
• Cho Kyuil
• Leschkies Kurtis
• Gouk Roman
• Buch Chintan
• Dicaprio Vincent

Classifications

• H10W70/698

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title

• H10W70/635 Primary

  Through-vias · CPC title

• H10W70/095 Primary

  of vias therein · CPC title

• H10W70/66

  Conductive materials thereof · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title