Semiconductor devices

Patent metadata

Field	Value
Publication number	US-10937700-B2
Application number	US-201715583167-A
Country	US
Kind code	B2
Filing date	May 1, 2017
Priority date	Nov 9, 2016
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

A semiconductor device includes a first semiconductor pattern doped with first impurities on a substrate, a first channel pattern on the first semiconductor pattern, second semiconductor patterns doped with second impurities contacting upper edge surfaces, respectively, of the first channel pattern, and a first gate structure surrounding at least a portion of a sidewall of the first channel pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first transistor on a substrate, the first transistor including:
a first semiconductor pattern doped with first impurities;
a first channel pattern on the first semiconductor pattern;
second semiconductor patterns contacting upper edge surfaces, respectively, of the first channel pattern, each of the second semiconductor patterns doped with second impurities; and
a first gate structure surrounding at least a portion of a sidewall of the first channel pattern; and

a second transistor on the substrate, the second transistor including:
a third semiconductor pattern doped with third impurities;
a second channel pattern on the third semiconductor pattern;
a fourth semiconductor pattern on the second channel pattern, the fourth semiconductor pattern doped with fourth impurities; and
a second gate structure surrounding at least a portion of a sidewall of the second channel pattern,

wherein the first and second impurities have different conductivity types from each other, and the third and fourth impurities have the same conductivity type as each other, and
wherein a first channel is generated in a direction parallel to an upper surface of the substrate in the first channel pattern, and a second channel is generated in a direction perpendicular to the upper surface of the substrate in the second channel pattern.

2. The semiconductor device of claim 1 , wherein the first channel pattern including a first channel with a first gate length, and the second channel pattern including a second channel with a second gate length, and wherein the first channel is formed in the direction parallel to the substrate surface, and the second channel is formed in the direction perpendicular to the substrate surface.

3. The semiconductor device of claim 2 , wherein the first gate length is greater than the second gate length.

4. The semiconductor device of claim 2 , wherein the first transistor comprises an input/output transistor, and the second transistor comprises a core transistor.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cantoro Mirco
• Lee Yun-Il
• Lee Hyung-Suk
• Heo Yeon-Cheol
• Kim Byoung-Gi
• Yoe Chang-Min
• Yun Seung-Chan
• Lee Dong-Hun

Classifications

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H10D62/213

  Channel regions of field-effect devices · CPC title

• H10D89/217

  comprising arrangements for charge injection in static induction transistor logic [SITL] devices · CPC title

• H10D84/834 Primary

  comprising FinFETs · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title