Integration of vertical transistors with 3D long channel transistors

Patent metadata

Field	Value
Publication number	US-9607899-B1
Application number	US-201615139478-A
Country	US
Kind code	B1
Filing date	Apr 27, 2016
Priority date	Apr 27, 2016
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A method for integrating a vertical transistor and a three-dimensional channel transistor includes forming narrow fins and wide fins in a substrate; forming a first source/drain (S/D) region at a base of the narrow fin and forming a gate dielectric layer and a gate conductor layer over the narrow fin and the wide fin. The gate conductor layer and the gate dielectric layer are patterned to form a vertical gate structure and a three-dimensional (3D) gate structure. Gate spacers are formed over sidewalls of the gate structures. A planarizing layer is deposited over the vertical gate structure and the 3D gate structure. A top portion of the narrow fin is exposed. S/D regions are formed on opposite sides of the 3D gate structure to form a 3D transistor, and a second S/D region is formed on the top portion of the narrow fin to form a vertical transistor.

First claim

What is claimed is:

1. A method for integrating a vertical transistor and a three-dimensional channel transistor, comprising:
forming narrow fins and wide fins in a substrate;
forming a first source/drain (S/D) region at a base of the narrow fin;
forming a gate dielectric layer and a gate conductor layer over the narrow fin and the wide fin;
depositing a top spacer on the gate conductor layer;
patterning the gate conductor layer and the gate dielectric layer to form a vertical gate structure over the narrow fin and a three-dimensional (3D) gate structure over the wide fin;
forming gate spacers over sidewalls of the vertical gate structure and over sidewalls of three-dimensional gate structure;
depositing a planarizing layer over the vertical gate structure and the 3D gate structure over the wide fin;
exposing a top portion of the narrow fin; and
forming S/D regions on opposite sides of the 3D gate structure to form a 3D transistor and a second S/D region on the top portion of the narrow fin to form a vertical transistor.

2. The method as recited in claim 1 , further comprising directionally depositing a spacer layer on the first S/D region.

3. The method as recited in claim 1 , wherein depositing the top spacer includes directionally depositing the top spacer.

4. The method as recited in claim 1 , wherein the vertical transistor includes a vertical gate length in a direction of a height of the narrow fin.

5. The method as recited in claim 1 , wherein the 3D transistor includes a gate length having a horizontal portion in a direction of a width of the wide fin and a vertical portion in a direction of a height of the wide fin.

6. The method as recited in claim 1 , further comprising forming shallow trench isolation regions between the vertical transistor and the 3D transistor.

7. The method as recited in claim 1 , wherein the S/D regions on opposite sides of the 3D gate structure are formed concurrently with the second S/D region.

8. The method as recited in claim 1 , further comprising annealing to form diffusion regions corresponding to the S/D regions on opposite sides of the 3D gate structure in the substrate.

9. A method for integrating a vertical transistor and a three-dimensional channel transistor, comprising:
implanting dopants to form wells in a substrate;
forming shallow trench isolation regions in the substrate;
etching narrow fins and wide fins in the substrate;
epitaxially growing a first source/drain region (S/D) at a base of the narrow fin;
depositing a first spacer layer on the first S/D region;
forming a gate dielectric layer and a gate conductor layer over the narrow fin and the wide fin;
depositing a second spacer on the gate conductor layer;
patterning the gate conductor layer and the gate dielectric layer to form a vertical gate structure over the narrow fin and a three-dimensional (3D) gate structure over the wide fin;
forming gate spacers over sidewalls of the vertical gate structure and over sidewalls of three-dimensional gate structure;
depositing a planarizing layer over the vertical gate structure and the 3D gate structure over the wide fin;
exposing a top portion of the narrow fin;
forming S/D regions on opposite sides of the 3D gate structure to form a 3D transistor and a second S/D region on the top portion of the narrow fin to form a vertical transistor;
depositing an interlevel dielectric (ILD) over the 3D transistor and the vertical transistor; and
forming contacts through the ILD down to the second S/D region and the S/D regions on opposite sides of the 3D gate structure.

10. The method as recited in claim 9 , further comprising directionally depositing the first spacer layer on the first S/D region.

11. The method as recited in claim 9 , wherein depositing the second spacer layer includes directionally depositing the second spacer layer.

12. The method as recited in claim 9 , wherein the vertical transistor includes a vertical gate length in a direction of a height of the narrow fin.

13. The method as recited in claim 9 , wherein the 3D transistor includes a gate length having a horizontal portion in a direction of a width of the wide fin and a vertical portion in a direction of a height of the wide fin.

14. The method as recited in claim 9 , wherein the S/D regions on opposite sides of the 3D gate structure are formed concurrently with the second S/D region.

15. The method as recited in claim 9 , further comprising annealing to form diffusion regions corresponding to the S/D regions on opposite sides of the 3D gate structure in the substrate.

16. An integrated device with vertical transistors and three-dimensional channel transistors, comprising:
a vertical transistor including:
a narrow fin vertical channel extending between vertically disposed source/drain (S/D) regions; and
a vertical gate structure formed about the narrow fin and including a gate dielectric and a gate conductor and having a vertical gate length in a direction of a height of the narrow fin; and

a three-dimensional (3D) transistor including:
a wide fin formed on a same substrate as the narrow fin; and
a 3D gate structure formed over the wide fin and including the gate dielectric and the gate conductor of the vertical gate structure and having a gate length having a horizontal portion in a direction of a width of the wide fin and a vertical portion in a direction of a height of the wide fin.

17. The device as recited in claim 16 , further comprising shallow trench isolation regions formed between the vertical transistor and the 3D transistor.

18. The device as recited in claim 16 , wherein the 3D transistor includes S/D regions formed on opposite sides of the 3D gate structure.

19. The device as recited in claim 18 , further comprising diffusion regions corresponding to the S/D regions on opposite sides of the 3D gate structure and formed in the substrate.

20. The device as recited in claim 16 , wherein the 3D transistor includes an analog device and the vertical transistor includes a logic device.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Miao Xin
• Xu Wenyu
• Zhang Chen

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title