Complementary metal-oxide semiconductor (cmos) transistor and tunnel field-effect transistor (tfet) on a single substrate

Patent metadata

Field	Value
Publication number	US-2016268256-A1
Application number	US-201514657021-A
Country	US
Kind code	A1
Filing date	Mar 13, 2015
Priority date	Mar 13, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

An apparatus includes a structure that includes a single substrate, a planar complementary metal-oxide semiconductor (CMOS) transistor formed on the single substrate, a planar tunnel field-effect transistor (TFET) formed on the single substrate, and a mobility enhancement strength layer included in the planar CMOS transistor or included in the planar TFET.

First claim

1 . An apparatus comprising a structure that includes:
a single substrate; a planar complementary metal-oxide semiconductor (CMOS) transistor formed on the single substrate; a planar tunnel field-effect transistor (TFET) formed on the single substrate; and a mobility enhancement strength layer included in the planar CMOS transistor or included in the planar TFET.

2 . The apparatus of claim 1 , wherein the mobility enhancement strength layer comprises at least one of silicon-carbide or silicon-germanium.

3 . The apparatus of claim 1 , wherein the mobility enhancement strength layer corresponds to an n-type source of the planar CMOS transistor or to an n-type drain of the planar CMOS transistor.

4 . The apparatus of claim 3 , wherein the n-type source and the n-type drain comprise silicon carbide.

5 . The apparatus of claim 1 , wherein the mobility enhancement strength layer corresponds to a p-type source of the planar CMOS transistor or to a p-type drain of the planar CMOS transistor.

6 . The apparatus of claim 5 , wherein the p-type source and the p-type drain comprise silicon germanium.

7 . The apparatus of claim 1 , wherein the mobility enhancement strength layer corresponds to a p-type source of the planar TFET or to an n-type drain of the planar TFET.

8 . The apparatus of claim 7 , wherein the p-type source comprises silicon germanium, and wherein the n-type drain comprises silicon carbide.

9 . The apparatus of claim 1 , wherein the mobility enhancement strength layer corresponds to an n-type source of the planar TFET or to a p-type drain of the planar TFET.

10 . The apparatus of claim 9 , wherein the n-type source comprises silicon carbide, and wherein the p-type drain comprises silicon germanium.

11 . An apparatus comprising a structure that includes:
a single substrate; a complementary metal-oxide semiconductor (CMOS) transistor formed on the single substrate; and a tunnel field-effect transistor (TFET) formed on the single substrate, at least one of the CMOS transistor or the TFET configured to support a current flow direction between a source and a drain that is perpendicular to the single substrate.

12 . The apparatus of claim 11 , wherein the CMOS transistor is a fin-shaped field effect transistor (finFET).

13 . The apparatus of claim 11 , further comprising:
a first n-type source and a first p-type source of the CMOS transistor; and a first n-type drain and a first p-type drain of the TFET, wherein the first n-type source, the first p-type source, the first n-type drain, and the first p-type drain are co-planar.

14 . The apparatus of claim 13 , further comprising:
a second n-type drain and a second p-type drain of the CMOS transistor; and a second p-type source and a second n-type source of the TFET, wherein the second n-type drain is aligned with the first n-type source, wherein the second p-type drain is aligned with the first p-type source, wherein the second p-type source is aligned with the first n-type drain, wherein the second n-type source is aligned with the first p-type drain, and wherein the second n-type drain, the second p-type drain, the second n-type source, and the second p-type source are co-planar.

15 . The apparatus of claim 14 , further comprising:
a first intrinsic layer of the CMOS transistor, the first intrinsic layer between the first re-type source and the second n-type drain; a second intrinsic layer of the CMOS transistor, the second intrinsic layer between the first p-type source and the second p-type drain; a third intrinsic layer of the TFET, the third intrinsic layer between the first n-type drain and the second p-type source; and a fourth intrinsic layer of the TFET, the fourth intrinsic layer between the first p-type drain and the second n-type source, wherein the first intrinsic layer, the second intrinsic layer, the third intrinsic layer, and the fourth intrinsic layer are co-planar.

16 . A method of forming a structure, the method comprising:
forming a complementary metal-oxide semiconductor (CMOS) transistor on a single substrate; and forming a tunnel field-effect transistor (TFET) on the single substrate, at least one of the CMOS transistor or the TFET configured to support a current flow direction between a source and a drain that is perpendicular to the single substrate.

17 . The method of claim 16 , wherein forming the CMOS transistor includes forming a first n-type source and a first p-type source on the single substrate, and wherein forming the TFET includes forming a first n-type drain and a first p-type drain on the single substrate.

18 . The method of claim 17 , wherein the first n-type source, the first n-type drain, the first p-type source, and the first p-type drain are co-planar.

19 . The method of claim 17 , wherein forming the CMOS transistor includes forming a second n-type drain on the first n-type source and forming a second p-type drain on the first p-type source, and wherein forming the TFET includes forming a second p-type source on the first n-type drain and forming a second n-type source on the first p-type drain.

20 . The method of claim 19 , wherein the second n-type drain, the second p-type source, the second p-type drain, and the second n-type source are co-planar.

21 . The method of claim 19 , wherein forming the CMOS transistor includes forming a first intrinsic layer on the first n-type source, wherein the second n-type drain is formed on the first intrinsic layer, wherein forming the TFET includes forming a second intrinsic layer on the first n-type drain, and wherein the second p-type source is formed on the second intrinsic layer.

22 . The method of claim 21 , wherein the first intrinsic layer and the second intrinsic layer are co-planar.

23 . The method of claim 19 , wherein forming the CMOS transistor includes forming a first intrinsic layer on the first p-type source, wherein the second p-type drain is formed on the first intrinsic layer, wherein forming the TFET includes forming a second intrinsic layer on the first p-type drain, and wherein the second n-type source is formed on the second intrinsic layer.

24 . The method of claim 23 , wherein the first intrinsic layer and the second intrinsic layer are co-planar.

25 . A method of forming a structure, the method comprising:
forming a planar complementary metal-oxide semiconductor (CMOS) transistor on a single substrate; and forming a planar tunnel field-effect transistor (TFET) on the single substrate, wherein at least one of the planar CMOS transistor or the planar TFET includes a mobility enhancement strength layer.

26 . The method of claim 25 , wherein the mobility enhancement strength layer comprises at least one of silicon-carbide or silicon-germanium.

27 . The method of claim 25 , further comprising forming a first n-type source, a first p-type source, a first n-type drain, and a first p-type drain of the planar CMOS transistor, wherein the mobility enhancement strength layer includes at least one of the first n-type source, the first p-type source, the first n-type drain, or the first p-type drain.

28 . The method of claim 25 , further comprising forming a second p-type source, a second n-type source, a second n-type drain, and a second p-type drain of the planar TFET, wherein the mobility enhancement strength layer includes at least one of th

Assignees

• Qualcomm Inc

Inventors

• Yang Bin
• Li Xia
• Yuan Jun

Classifications

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D30/0275

  forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title