Series connected transistor structure and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9373620-B2
Application number	US-201414485541-A
Country	US
Kind code	B2
Filing date	Sep 12, 2014
Priority date	Sep 12, 2014
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.

First claim

What is claimed is:

1. A series-connected transistor structure, comprising:
a first source over a substrate;
a first channel-drain structure over the first source, the first channel-drain structure comprising a first channel and a first drain over the first channel;
a second channel-drain structure over the first source and substantially parallel to the first channel-drain structure, the second channel-drain structure comprising a second channel and a second drain over the second channel;
a gate dielectric layer surrounding the first channel and the second channel;
a continuous gate surrounding the gate dielectric layer and between the first channel and the second channel;
a first drain pad over and in contact with the first drain;
a second drain pad over and in contact with the second drain, wherein the first drain pad and the second drain pad are separated from each other and the first drain pad is series connected to the second drain pad through the first channel-drain structure, the first source and the second channel-drain structure; and
two conductive plugs separated from each other and respectively connected to the first drain pad and the second drain pad.

2. The series-connected transistor structure of claim 1 , further comprising a source dielectric layer between the first source and the continuous gate.

3. The series-connected transistor structure of claim 2 , further comprising a high-k dielectric layer between the gate dielectric layer and the continuous gate and between the source dielectric layer and the continuous gate.

4. The series-connected transistor structure of claim 1 , further comprising a source silicide region in the first source.

5. The series-connected transistor structure of claim 4 , further comprising a source dielectric layer between the first source and the continuous gate, and the source silicide region is in contact with the source dielectric layer.

6. The series-connected transistor structure of claim 1 , wherein at least one of the first drain pad and the second drain pad comprises metal or silicide.

7. The series-connected transistor structure of claim 1 , further comprising an inter-layer dielectric (ILD) covering the continuous gate and exposing an upper surface of the first drain and an upper surface of the second drain.

8. The series-connected transistor structure of claim 7 , wherein the first drain pad and the second drain pad are over the ILD.

9. The series-connected transistor structure of claim 7 , wherein the ILD is between the first drain and the second drain.

10. The series-connected transistor structure of claim 7 , further comprising another ILD over and between the first drain pad and the second drain pad.

11. The series-connected transistor structure of claim 10 , wherein the two conductive plugs are through the other ILD.

12. The series-connected transistor structure of claim 1 , wherein the first drain has a width greater than a width of the first channel.

13. The series-connected transistor structure of claim 1 , wherein the second drain has a width greater than a width of the second channel.

14. The series-connected transistor structure of claim 1 , wherein the first source has two protruding portions respectively in contact with the first channel and the second channel.

15. The series-connected transistor structure of claim 14 , wherein one of the two protruding portions in contact with the first channel has a width greater than a width of the first channel.

16. The series-connected transistor structure of claim 15 , wherein the other of the two protruding portions in contact with the second channel has a width greater than a width of the second channel.

17. The series-connected transistor structure of claim 14 , further comprising a source dielectric layer between the two protruding portions.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Chin-Chi
• Lee Chien-Chih
• Chiang Tien-Wei
• Tsai Ching-Wei
• Wang Chih-Ching
• Ho Jon-Hsu
• Hsieh Wen-Hsing

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/60

  of insulating materials · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/43

  Layouts of interconnections · CPC title