Vertical NAND device containing peripheral devices on epitaxial semiconductor pedestal

Patent metadata

Field	Value
Publication number	US-9305934-B1
Application number	US-201414517134-A
Country	US
Kind code	B1
Filing date	Oct 17, 2014
Priority date	Oct 17, 2014
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A multilevel structure includes a stack of an alternating plurality of electrically conductive layers and insulator layers located over a semiconductor substrate, and an array of memory stack structures located within memory openings through the stack. An epitaxial semiconductor pedestal is provided, which is in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate and has a top surface within a horizontal plane located above a plurality of electrically conductive layers within the stack. The contact via structures for the semiconductor devices on the epitaxial semiconductor pedestal can extend can be less than the thickness of the stack.

First claim

What is claimed is:

1. A multilevel structure, comprising:
a stack of an alternating plurality of electrically conductive layers and insulator layers located over a semiconductor substrate;
an array of memory stack structures located within memory openings through the stack; and
an epitaxial semiconductor pedestal in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate and having a top surface within a horizontal plane located above a plurality of electrically conductive layers within the stack.

2. The multilevel structure of claim 1 , further comprising at least one semiconductor device located on the top surface of the epitaxial semiconductor pedestal.

3. The multilevel structure of claim 2 , wherein the at least one semiconductor device comprises a field effect transistor, and a gate electrode of the field effect transistor protrudes above another horizontal plane including a topmost surface of the stack.

4. The multilevel structure of claim 3 , comprising an array of drain regions contacting a respective semiconductor channel within the array of memory stack structures.

5. The multilevel structure of claim 4 , further comprising at least one dielectric liner contacting an active region of the field effect transistor and having a top surface that is coplanar with top surfaces of the drain regions.

6. The multilevel structure of claim 4 , wherein a bottom surface of each drain region is located above the horizontal plane including the top surface of the epitaxial semiconductor pedestal.

7. The multilevel structure of claim 4 , further comprising a dielectric material layer overlying the epitaxial semiconductor pedestal and laterally surrounding the gate electrode of the field effect transistor, wherein a top surface of the dielectric material layer is coplanar with top surfaces of the drain regions.

8. The multilevel structure of claim 3 , wherein a vertical offset distance between the top surface of the epitaxial semiconductor pedestal and a topmost surface of the stack does not exceed a thickness of a gate dielectric of the field effect transistor.

9. The multilevel structure of claim 2 , further comprising:
at least one dielectric material layer overlying the stack and the at least one semiconductor device; and
at least one contact via structure extending through the at least one dielectric material layer, wherein a bottommost surface of the at least one contact via structure is located above a horizontal plane including a bottom surface of a topmost electrically conductive layer within the stack.

10. The multilevel structure of claim 1 , wherein the top surface of the epitaxial semiconductor pedestal is located above another horizontal plane including a bottom surface of a topmost electrically conductive layer within the stack.

11. The multilevel structure of claim 1 , wherein the top surface of the epitaxial semiconductor pedestal is located above another horizontal plane including a bottom surface of a topmost insulator layer within the stack.

12. The multilevel structure of claim 1 , further comprising a stepped dielectric material portion in contact with a sidewall of the epitaxial semiconductor pedestal and overlying the substrate.

13. The multilevel structure of claim 1 , wherein the top surface of the epitaxial semiconductor pedestal is coplanar with a topmost surface of the stack.

14. The multilevel structure of claim 1 , further comprising a device located on the semiconductor substrate, wherein:
the device comprises a vertical NAND device located in a device region; and
at least one of the electrically conductive layers in the stack comprises, or is electrically connected to, a word line of the NAND device.

15. The multilevel structure of claim 14 , wherein:
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
a plurality of electrically conductive layers in the stack is in electrical contact with the plurality of control gate electrodes and extends from the device region to a contact region including the plurality of electrically conductive contact via structures.

16. A method of fabricating a multilevel structure, comprising:
forming a stack including an alternating plurality of material layers and insulator layers over a semiconductor substrate;
forming an opening through the stack, wherein a top surface of the semiconductor substrate is exposed at a bottom of the opening;
forming, within the opening, an epitaxial semiconductor pedestal in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate;
forming an array of memory openings through the stack after formation of the epitaxial semiconductor pedestal; and
forming an array of memory stack structures within the array of memory openings.

17. The method of claim 16 , wherein the epitaxial semiconductor pedestal is formed by:
depositing, within the opening, a single crystalline semiconductor material in epitaxial alignment with the single crystalline substrate semiconductor material within the substrate; and
recessing a top surface of the deposited single crystalline semiconductor material to a height that is not lower than a topmost surface of the stack.

18. The method of claim 17 , wherein the recessing of the top surface of the deposited single crystalline semiconductor material is performed by chemical mechanical planarization.

19. The method of claim 17 , wherein the topmost surface of the stack is employed as a stopping layer during planarization of the top surface of the deposited single crystalline semiconductor material.

20. The method of claim 17 , wherein the material layers comprises silicon nitride or a semiconductor material including at least one of silicon and germanium.

21. The method of claim 16 , further comprising forming at least one semiconductor device on a top surface of the epitaxial semiconductor pedestal.

22. The method of claim 21 , wherein the at least one semiconductor device comprises a field effect transistor.

23. The method of claim 16 , wherein a top surface of the epitaxial semiconductor pedestal is formed above a horizontal plane including a bottom surface of a topmost electrically conductive layer within the stack.

24. The method of claim 16 , wherein a top surface of the epitaxial semiconductor pedestal is formed above another horizontal plane including a bottom surface of a topmost insulator layer within the stack.

25. The method of claim 16 , wherein each of the memory stack structures comprises:
a memory film including a charge trapping layer; and
a semiconductor channel including a portion that extends vertically from a top surface of the semiconductor substrate.

26. The method of claim 16 , further c

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Inc

Inventors

• Ding Hao
• Yaegashi Masahiro
• Fujino Shigehiro
• Minagawa Shuji
• Fukano Yuji

Classifications

• H10D30/63 Primary

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H01L21/02532

  Electricity · mapped topic

• H01L21/30625

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11526

  Electricity · mapped topic