Three-dimensional semiconductor memory device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9997530-B2
Application number	US-201514708477-A
Country	US
Kind code	B2
Filing date	May 11, 2015
Priority date	Jun 23, 2014
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.

First claim

What is claimed is:

1. A three-dimensional semiconductor memory device, comprising:
a substrate;
a peripheral circuit structure on the substrate;
a horizontal active layer on the peripheral circuit structure, the horizontal active layer comprising first, second, and third active semiconductor layers sequentially stacked on the substrate, such that the second active semiconductor layer directly contacts the first active semiconductor layer and the third active semiconductor layer directly contacts the second active semiconductor layer, the first active semiconductor layer being doped with p-type impurities to have a first concentration, the third active semiconductor layer being doped with p-type impurities to have a second concentration lower than the first concentration or being in an undoped state, and the second active semiconductor layer comprising an impurity diffusion restraining material;
a plurality of stacks provided parallel to a first direction on the horizontal active layer, each of the stacks comprising a plurality of electrodes vertically stacked on the horizontal active layer, such that the horizontal active layer is between the substrate and lowermost electrodes of the plurality of electrodes; and
vertical structures arranged on the horizontal active layer and penetrating the stacks.

2. The device of claim 1 , wherein each of the vertical structures comprises a vertical channel pattern connected to the horizontal active layer and a memory pattern disposed between the vertical channel pattern and each respective one of the stacks, and the memory pattern comprises a charge storing layer.

3. The device of claim 1 , wherein each of the vertical structures comprises a vertical-pillar-shaped electrode connected to the horizontal active layer and a memory pattern disposed between the vertical-pillar-shaped electrode and a respective one of the stacks, and the memory pattern comprises a material exhibiting a variable resistance property.

4. The device of claim 1 , wherein the substrate comprises a cell array region and a connection region positioned around the cell array region, and
the stacks are disposed on the cell array region and the connection region, and each of the stacks has a stepwise sidewall profile on the connection region.

5. The device of claim 4 , further comprising a common source region in the horizontal active layer between ones of the stacks and extends parallel to the first direction.

6. The device of claim 4 , further comprising pick-up regions in the horizontal active layer and on the connection region that are connected to the first active semiconductor layer,
wherein the pick-up regions are doped with p-type impurities and are disposed adjacent to the stacks.

7. The device of claim 6 , further comprising pick-up diffusion barrier regions disposed in the third active semiconductor layer to surround the pick-up regions, respectively, wherein the pick-up diffusion barrier regions comprise carbon.

8. The device of claim 1 , further comprising contacts connected to the peripheral circuit structure and the first active semiconductor layer, respectively.

9. The device of claim 1 , wherein the peripheral circuit structure comprises a peripheral circuit device on the substrate and a peripheral interconnection structure connected to the peripheral circuit device.

10. The device of claim 1 , wherein the impurity diffusion restraining material contains carbon.

11. The device of claim 1 , wherein the horizontal active layer further comprises a buffer insulating layer and a fourth active semiconductor layer that are sequentially provided on the third active semiconductor layer.

12. A three-dimensional semiconductor memory device, comprising:
a substrate;
a peripheral circuit device on the substrate;
a lower mold insulating layer covering the peripheral circuit device;
a horizontal active layer on the lower mold insulating layer; and
a cell array structure on the horizontal active layer,
wherein the cell array structure comprises a plurality of stacks provided parallel to each other, vertical structures penetrating the stacks, and a common source region of a second conductivity type being provided between ones of the stacks and extending parallel to the stacks, and
wherein the horizontal active layer comprises a first active semiconductor layer, an impurity diffusion barrier layer, and a second active semiconductor layer sequentially stacked on the lower mold insulating layer, such that the impurity diffusion barrier layer directly contacts the first active semiconductor layer and the second active semiconductor layer directly contacts the impurity diffusion barrier layer,
the first active semiconductor layer is doped with impurities to have a first conductivity type and a first concentration,
the second active semiconductor layer is doped with impurities to have the first conductivity type and a second concentration lower than the first concentration or is in an undoped state, and
the impurity diffusion barrier layer comprises a material that inhibits diffusion of the impurities doped in the first active semiconductor layer into the second active semiconductor layer;
wherein the horizontal active layer is between the substrate and lowermost electrodes of a plurality of electrodes of ones of the stacks.

13. The device of claim 12 , further comprising a peripheral interconnection structure in the lower mold insulating layer and connected to the peripheral circuit device.

14. The device of claim 12 , further comprising first semiconductor patterns disposed below the vertical structures, respectively, to be in contact with the second active semiconductor layer.

15. The device of claim 12 , wherein the common source region is a second semiconductor pattern disposed on the horizontal active layer.

16. The device of claim 12 , wherein the horizontal active layer further comprises a buffer insulating layer and a third active semiconductor layer sequentially stacked on the second active semiconductor layer.

17. The device of claim 16 , further comprising semiconductor patterns disposed below the vertical structures, respectively,
wherein the semiconductor patterns penetrate the third active semiconductor layer and the buffer insulating layer and are in contact with the second active semiconductor layer, and the common source region is disposed in the third active semiconductor layer.

18. A three-dimensional semiconductor memory device, comprising:
a substrate;
a peripheral circuit structure on the substrate, the peripheral circuit structure comprising a lower mold insulating layer covering a peripheral circuit device; and
a horizontal active layer on the peripheral circuit structure and electrically connected to the peripheral circuit structure, the horizontal active layer comprising carbon, the horizontal active layer further comprising a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer sequentially stacked on the substrate, such that the second semiconductor layer directly contacts the first semiconductor layer and the third semiconductor layer directly contacts the second semiconductor layer;
wherein the peripheral circuit structure and the horizontal active layer are stacked in a first direction that is perpendicular to a top surface of the substrate,
wherein the first, second and third semiconductor layers extend along second and third directions that cross each other and are parallel with the top surface of the substrate, and
wherein the second semiconductor layer contains carbo

Assignees

• Yon Gukhyon
• Kim Dongwoo
• Hwang Kihyun
• Kim Dongkyum
• Yoo Dongchul
• Samsung Electronics Co Ltd

Inventors

• Yon Gukhyon
• Kim Dongwoo
• Hwang Kihyun
• Kim Dongkyum
• Yoo Dongchul

Classifications

• H01L45/1226

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• H01L27/11578

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic