Memory device and in-memory search method thereof
US-2024274164-A1 · Aug 15, 2024 · US
Erase operation for 3D non-volatile memory with controllable gate-induced drain leakage current
US9019775B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9019775-B2 |
| Application number | US-201213450313-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 18, 2012 |
| Priority date | Apr 18, 2012 |
| Publication date | Apr 28, 2015 |
| Grant date | Apr 28, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for performing an erase operation in a 3D stacked non-volatile memory device, comprising: performing each erase iteration of a plurality of erase iterations of the erase operation for a set of memory cells in at least one NAND string, the at least one NAND string comprises a drain-side end in communication with a bit line, and a select gate, drain (SGD) transistor, the SGD transistor comprises a drain in communication with the drain-side end, and th…
Assignees
Inventors
Classifications
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G11C5/02Primary
Physics · mapped topic
- G11C16/0483Primary
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9019775B2 cover?
- An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase …
- Who is the assignee on this patent?
- Costa Xiying, Li Haibo, Higashitani Masaaki, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification G11C5/02. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 28 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).