Equalizing erase depth in different blocks of memory cells

Patent metadata

Field	Value
Publication number	US-9786378-B1
Application number	US-201615367549-A
Country	US
Kind code	B1
Filing date	Dec 2, 2016
Priority date	Dec 2, 2016
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A memory device and associated techniques provide a uniform erase depth for different blocks of memory cells which are at different distances from pass gates of a voltage source. In one approach, a voltage of a source side select gate transistor of a memory string is a decreasing function of the distance. In another approach, a magnitude or duration of an erase voltage at a source end of a memory string is an increasing function of the distance. Adjacent blocks can be arranged in subsets and treated as being at a common distance. In another approach, an additional erase pulse can be applied when the distance of the block exceeds a threshold. Other variables such as initial erase voltage and step size can also be adjusted as a function of distance.

First claim

We claim:

1. An apparatus, comprising:
a plurality of blocks of memory cells, the memory cells are arranged in strings, each string comprising a source end, a drain end, a channel extending between the source end and the drain end, and a select gate transistor at the source end;
a voltage source which comprises a pass gate and which provides a select gate voltage;
a voltage source which provides a source end voltage; and
a control circuit, the control circuit configured to, in an erase operation for a selected block among the plurality of blocks, connect the select gate voltage to the select gate transistors and connect the source end voltage to the source ends to charge up the channel of each string of the selected block by gate-induced drain leakage, wherein each select gate transistor has a positive channel-to-control gate voltage and a magnitude of the source end voltage minus the select gate voltage is based on an increasing function of a distance of the selected block from the pass gate.

2. The apparatus of claim 1 , wherein:
the control circuit is configured to increase the source end voltage by a step size in erase loops; and
an initial magnitude of the source end voltage in the erase loops is based on an increasing function of the distance.

3. The apparatus of claim 1 , wherein:
the control circuit is configured to increase the source end voltage by a step size in erase loops; and
the step size is an increasing function of the distance.

4. The apparatus of claim 1 , wherein:
a duration of the source end voltage is based on an increasing function of the distance.

5. The apparatus of claim 1 , wherein:
the control circuit is configured to set a duration of the source end voltage based on an increasing function of the distance in response to a determination that a temperature is below a threshold.

6. The apparatus of claim 1 , wherein:
a duration of the source end voltage is based on an increasing function of the distance.

7. The apparatus of claim 1 , wherein:
the memory cells are connected to word lines; and
the control circuit, in the erase operation, is configured to apply a voltage to the word lines which is based on a decreasing function of the distance.

8. The apparatus of claim 1 , wherein:
the control circuit, to perform the erase operation, is configured to connect the select gate voltage to the select gate transistors and connect the source end voltage to the source ends in a series of erase loops, and to perform a verify test in each erase loop, wherein after the verify test is passed, the control circuit is configured to provide an additional erase pulse to the selected block if the distance exceeds a threshold.

9. The apparatus of claim 1 , wherein:
the magnitude is lowest for a block which is closest to the pass gate and highest for a block which is further from the pass gate.

10. The apparatus of claim 1 , wherein:
a magnitude of the source end voltage is independent of the distance.

11. The apparatus of claim 1 , wherein:
the memory cells are connected to word lines; and
the control circuit, in the erase operation, is configured to set a control gate voltage for the memory cells which is less than the select gate when the channel of each string is charged up.

12. The apparatus of claim 1 , wherein:
the control circuit is configured to set a magnitude of the source end voltage based on an increasing function of the distance in response to a determination that a temperature is above a threshold.

13. The apparatus of claim 1 , wherein:
the source end of each string of the selected block comprises a source diffusion region which is common to the plurality of blocks; and
the control circuit is configured to provide a common magnitude and duration of the source end voltage during erase operations for each of the plurality of blocks.

14. A method, comprising:
in connection with an erase operation of a selected block of memory cells, wherein the memory cells are arranged in strings, each string comprising a source end, a drain end, a channel extending between the source end and the drain end, and a select gate transistor:
providing a pass gate of a voltage source in a conductive state to pass a select gate voltage from the voltage source to each select gate transistor while providing a source end voltage to the source end of each string, wherein the select gate voltage is based on a function of a distance between the pass gate and the selected block.

15. The method of claim 14 , wherein:
a magnitude of the select gate voltage is based on a decreasing function of the distance.

16. The method of claim 14 , wherein:
a duration of the select gate voltage is based on an increasing function of the distance.

17. The method of claim 14 , wherein:
the selected block is among a plurality of blocks, each block of the plurality of blocks is at a different distance from the pass gate, the blocks are in subsets and a different select gate voltage is cross-referenced to each subset.

18. The method of claim 14 , wherein:
the source end voltage is independent of the distance.

19. An apparatus, comprising:
a block of memory cells which is selected to undergo an erase operation, the memory cells are arranged in strings, each string comprising a source end, a drain end, a channel extending between the source end and the drain end, and a select gate transistor at the drain end;
means for providing a select gate voltage to the select gate transistors in the erase operation; and
means for providing a source end voltage to the source ends in the erase operation, the source end voltage has a duration which is based on an increasing function of a distance between the block and the means for providing the select gate voltage in response to a determination that a temperature is below a threshold, and the source end voltage has a magnitude which is based on an increasing function of the distance in response to a determination that the temperature is above a threshold.

20. The apparatus of claim 19 , wherein:
the magnitude and/or duration of the source end voltage is set to equalize an erase depth for the block relative to an erase depth of another block having another distance to the means for providing the select gate voltage.

Assignees

• Sandisk Technologies Llc

Inventors

• Zhang Zhengyi
• Pang Liang
• Zeng Caifu
• Yu Xuehong
• Dong Yingda

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10

  Programming or data input circuits · CPC title