Nonvolatile memory device configured to adjust a read parameter based on degradation level

Patent metadata

Field	Value
Publication number	US-10910080-B2
Application number	US-202016865675-A
Country	US
Kind code	B2
Filing date	May 4, 2020
Priority date	Mar 14, 2018
Publication date	Feb 2, 2021
Grant date	Feb 2, 2021

Abstract

A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

First claim

What is claimed is:

1. A nonvolatile memory device, comprising:
a page buffer including a plurality of latch sets that latch respective page data of memory cells according to respective read signal sets, the read signal sets including a prior read signal set and subsequent read signal sets; and
control logic configured to,
detect a degradation level of the memory cells by one or more of (i) comparing a current count value of the memory cells between a plurality of read signals included in the prior read signal set with an initial count value of the memory cells distributed between the plurality of read signals, and (ii) comparing a current difference value of the memory cells between the plurality of read signals included in the prior read signal set with an initial difference value of the memory cells distributed between the plurality of read signals, and
determine a read parameter applied to the subsequent read signal sets based on the degradation level of the memory cells detected based on a result of the comparing using the prior read signal set.

2. The nonvolatile memory device of claim 1 , wherein a reference degradation level includes a first reference degradation level and a second reference degradation level higher than the first reference degradation level, and
the control logic is configured to compare the degradation level with the first reference degradation level to determine a number of read signals in each of the read signal sets, the read signal sets each including at least one read signal.

3. The nonvolatile memory device of claim 1 , wherein a reference degradation level includes a first reference degradation level and a second reference degradation level higher than the first reference degradation level, and
the control logic is configured to compare the degradation level with the second reference degradation level to determine levels of read signals in each of the read signal sets.

4. The nonvolatile memory device of claim 1 , wherein the read parameter includes a reference value defining an error exclusion range of a result of at least one read operation such that a level of the reference value increases as the degradation level of the memory cells increases.

5. The nonvolatile memory device of claim 4 , wherein the level of the reference value increases stepwise.

6. The nonvolatile memory device of claim 1 , wherein the subsequent read signal sets includes a first subsequent read signal set and a second subsequent read signal set, and
the control logic is configured to detect the degradation level of the memory cells based on the first subsequent read signal set, and to determine a read parameter applied to the second subsequent read signal set based on the degradation level detected based on the first subsequent read signal set.

7. The nonvolatile memory device of claim 1 , wherein the control logic is configured to,
detect the degradation level of the memory cells by providing a degradation detection signal preceding the prior read signal set to a word line of the memory cells, and
determine the read parameter applied to the prior read signal set based on the degradation level.

8. The nonvolatile memory device of claim 7 , wherein the control logic is configured to,
set one reference degradation level applied equally to the memory cells,
obtain the degradation level of the memory cells by inputting the degradation detection signal to the memory cells, and
determine a read parameter for the memory cells by comparing the degradation level of the memory cells with the one reference degradation level.

9. A nonvolatile memory device, comprising:
a page buffer including a plurality of latch sets that latch respective page data of memory cells according to respective read signal sets, the read signal sets including a prior read signal set and subsequent read signal sets; and
control logic configured to, for each read operation of memory cells connected to different word lines among word lines connected to the memory cells,
detect a degradation level of the memory cells by one or more of (i) comparing a current count value of the memory cells between a plurality of read signals included in the prior read signal set with an initial count value of the memory cells distributed between the plurality of read signals, and (ii) comparing a current difference value of the memory cells between the plurality of read signals included in the prior read signal set with an initial difference value of the memory cells distributed between the plurality of read signals, and
determine a read parameter applied to the subsequent read signal sets based on the degradation level detected based on a result of the comparing using the prior read signal set.

10. The nonvolatile memory device of claim 9 , wherein read parameters corresponding to degradation levels are set to a Look-up Table, and the control logic is configured to determine the read parameters included in each of the read signal sets by referring to the Look-up Table according to the degradation level.

11. A nonvolatile memory device, comprising:
a page buffer unit connected to a memory cell array including a plurality of memory cells, the page buffer unit including a plurality of page buffers configured to store page data of the memory cells; and
control logic configured to group the page buffers into a plurality of count sections, and to define an error exclusion range of a read operation of the memory cells based on a count value of at least one of the plurality of count sections.

12. The nonvolatile memory device of claim 11 , wherein the control logic is configured to compare a count value of the at least one of the plurality of count sections with a maximum countable value of the at least one of the plurality of count sections.

13. The nonvolatile memory device of claim 12 , wherein the control logic is configured to determine a reference value corresponding to the maximum countable value as a final reference value in response to the count value of the at least one of the plurality of count sections being smaller than the maximum countable value.

14. The nonvolatile memory device of claim 12 , wherein the control logic is configured to compare a count value of a next count section of the plurality of count sections with a maximum countable value of the next count section, in response to the at least one of the plurality of count values being greater than or equal to the maximum countable value.

15. The nonvolatile memory device of claim 14 , wherein the maximum countable value and a reference value corresponding to the maximum countable value of the next count section are greater than the maximum countable value and a reference value corresponding to the maximum countable value of a previous count section of the plurality of count sections, respectively.

16. The nonvolatile memory device of claim 11 , wherein the control logic is configured to compare a count value of one count section of the plurality of count sections with a first maximum countable value.

17. The nonvolatile memory device of claim 16 , wherein the control logic is configured to determine a reference value corresponding to the first maximum countable value as a final reference value, in response to the count value of the one count section being smaller than the first maximum countable value.

18. The nonvolatile memory device of claim 16 , wherein the control logic is configured to compare the count value with a second maximum countable value, in response to the count value of the one count section being greater t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Bang Jin Bae
• Song Seung Hwan
• Byeon Dae Seok
• Park Il Han
• Yoon Hyun Jun
• Lee Han Jun
• Choi Na Young

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G11C29/50004

  of threshold voltage · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title