Storage device including dummy word lines and operating method thereof
US-2026057947-A1 · Feb 26, 2026 · US
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Choi Na-Young patents
Choi Na-Young is listed as an inventor on 6 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Choi Na-Young |
| Total patents | 6 |
| First publication | Sep 13, 2018 |
| Latest publication | Feb 26, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Memory device including a circuit for detecting word line defect and operating method thereof
US-10854250-B2 · Dec 1, 2020 · US
Methods of operating a nonvolatile memory device and the nonvolatile memory device thereof
US-10332607-B2 · Jun 25, 2019 · US
Memory device including a circuit for detecting word line defect and operating method thereof
US-2019130953-A1 · May 2, 2019 · US
Non-volatile memory device for reading data with optimized read voltage
US-10163518-B2 · Dec 25, 2018 · US
Methods of operating a nonvolatile memory device and the nonvolatile memory device thereof
US-2018261296-A1 · Sep 13, 2018 · US
Recent patents
Latest publications not already listed above.
No data yet.
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Samsung Electronics Co Ltd | 6 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C16/0483 | 6 |
| G11C16/08 | 6 |
| G11C16/30 | 6 |
| G11C16/10 | 6 |
| G11C16/28 | 3 |