Memory system including a memory device, and methods of operating the memory system and the memory device

Patent metadata

Field	Value
Publication number	US-9728279-B2
Application number	US-201414456572-A
Country	US
Kind code	B2
Filing date	Aug 11, 2014
Priority date	Aug 14, 2013
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A method is provided for operating a memory device. The method includes counting, from among memory cells, a number of first off-cells with respect to a first reading voltage and a number of second off-cells with respect to a second reading voltage, comparing the number of first off-cells and the number of second off-cells, and determining, based on a result of the comparing, whether a programming error exists in a storage region in which the memory cells are included.

First claim

What is claimed is:

1. A method of operating a memory device, the method comprising:
counting, from among memory cells, a number of first off-cells with respect to a first reading voltage and a number of second off-cells with respect to a second reading voltage;
comparing the counted number of first off-cells and the number of second off-cells; and
determining, based on a result of the comparing, whether a programming error exists in a storage region in which the memory cells are included,
wherein the first off-cells at least partially overlap the second off-cells.

2. The method of claim 1 ,
wherein a voltage level of the first reading voltage is higher than a voltage level of the second reading voltage.

3. The method of claim 1 ,
wherein the first reading voltage corresponds to a highest state from among a plurality of states in which the memory cells are programmed.

4. The method of claim 3 ,
wherein the second reading voltage corresponds to a second highest state from the plurality of states in which the memory cells are programmed.

5. The method of claim 1 ,
wherein the first reading voltage and the second reading voltage respectively correspond to a first state and a second state from among a plurality of states in which the memory cells are programmed,
wherein the first state is a state in which a memory cell is programmed last, and the second state is a state to which a memory cell is programmed before the first state.

6. The method of claim 1 ,
wherein comparing of the numbers of first and second off-cells comprises calculating a ratio of the number of first off-cells with respect to the first reading voltage to the number of second off-cells with respect to the second reading voltage.

7. The method of claim 1 , wherein in comparing the numbers of first and second off-cells comprises:
calculating numbers of memory cells in which a reading error is generated with respect to a first state corresponding to the first reading voltage and a second state corresponding to the second reading voltage, respectively; and
comparing reading error generation amounts of the first state and the second state.

8. The method of claim 1 ,
wherein determining whether a programming error exists comprises determining that a sudden power-off has occurred during an operation of programming the memory cells when the programming error is detected.

9. The method of claim 1 ,
wherein the memory cells include multi-bit memory cells.

10. A memory system, comprising:
a memory device comprising a memory cell array including memory cells arranged in storage regions;
a memory controller configured to perform control operations with respect to the memory device, including programming and reading data; and
a programming error detector configured to determine whether a programming error exists with respect to a memory cell in a storage region by comparing counted numbers of memory cells included in different states in which the memory cells are programmed.

11. The memory system of claim 10 , wherein the programming error detector comprises:
an off-cell counter configured to receive first data and second data, and to count a number of first off-cells with respect to a first reading voltage corresponding to a first state and a number of second off-cells with respect to a second reading voltage corresponding to a second state, wherein the first data indicates respective states of memory cells read based on the first reading voltage and the second data indicates respective states of memory cells read based on the second reading voltage;
a comparator configured to compare the number of first off-cells and the number of second off-cells, or to compare a variation of the number of first off-cells and a variation of the number of second off-cells, and to determine a comparison result; and
a programming error determiner configured to determine whether the storage region includes a programming error based on the comparison result.

12. The memory system of claim 11 ,
wherein when the comparator compares the number of first off-cells and the number of second off-cells, the comparing comprises calculating a ratio of the number of first off-cells to the number of second off-cells to determine the comparison result.

13. The memory system of claim 12 ,
wherein the programming error determiner is configured to determine that the storage region includes the programming error when the comparison result is less than a predetermined determination reference value.

14. The memory system of claim 11 ,
wherein when the comparator compares the variation of the number of first off-cells and the variation of the number of second off-cells, the comparing comprises calculating a ratio of the variation of the number of first off-cells to the variation of the number of second off-cells to determine the comparison result.

15. The memory system of claim 14 ,
wherein the programming error determiner is configured to determine that the storage region includes a programming error when the comparison result is greater than a predetermined determination reference value.

16. A method of operating a memory device, the method comprising:
counting, from among memory cells, a number of first off-cells with respect to a first reading voltage and a number of second off-cells with respect to a second reading voltage;
comparing the number of first off-cells and the number of second off-cells; and determining, based on a result of the comparing, whether a programming error exists in a storage region in which the memory cells are included,
wherein the first reading voltage and the second reading voltage respectively correspond to a first state and a second state from among a plurality of states in which the memory cells are programmed, and
wherein the first state is a state in which a memory cell is programmed last, and the second state is a state to which a memory cell is programmed before the first state.

17. The method of claim 16 ,
wherein comparing of the numbers of first and second off-cells comprises calculating a ratio of the number of first off-cells with respect to the first reading voltage to the number of second off-cells with respect to the second reading voltage.

18. The method of claim 17 , further comprising:
determining that the storage region includes the programming error when the comparison result is less than a predetermined determination reference value.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yim Hye-Jin
• Yoon Sang-Yong

Classifications

• G11C16/3418 Primary

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C16/3431

  Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step · CPC title

• G11C16/34 Primary

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title