Stacked semiconductor package assemblies including double sided redistribution layers

Patent metadata

Field	Value
Publication number	US-10886263-B2
Application number	US-201715721257-A
Country	US
Kind code	B2
Filing date	Sep 29, 2017
Priority date	Sep 29, 2017
Publication date	Jan 5, 2021
Grant date	Jan 5, 2021

Abstract

A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.

First claim

What is claimed is:

1. A semiconductor device package comprising:
a bottom electronic device having an active surface and a back surface opposite to the active surface;
an interposer module including a plurality of conductive vias and having a top surface and a bottom surface, wherein the conductive vias of the interposer module have different diameters, wherein the top surface of the interposer module is not leveled with the active surface of the bottom electronic device, and wherein the bottom surface of the interposer module is not leveled with the back surface of the bottom electronic device;
a top electronic device having an active surface and disposed above the bottom electronic device and above the interposer module;
a package body encapsulating the bottom electronic device and the interposer module and having a top surface and a bottom surface, wherein the top surface of the interposer module is leveled with the top surface of the package body, and wherein the bottom surface of the interposer module is leveled with the bottom surface of the package body; and
a double sided redistribution layer (RDL) structure disposed between the bottom electronic device and the top electronic device, the active surface of the bottom electronic device facing toward the double sided RDL structure, the active surface of the top electronic device facing toward the double sided RDL structure, the double sided RDL structure electrically connecting the active surface of the bottom electronic device to the active surface of the top electronic device, the double sided RDL structure electrically connecting the active surface of the top electronic device to the interposer module, the double sided RDL comprising:
a first RDL structure,
a second RDL structure disposed under the first RDL structure and
embedded under the top surface of the package body, and
a single dielectric layer between the active surface of the bottom electronic device and the active surface of the top electronic device, the single dielectric layer comprising a top surface exposing the first RDL structure and a bottom surface in direct contact with the second RDL structure, the bottom surface of the single dielectric layer being further in contact with the interposer module allowing the top electronic device and the bottom electronic device to communicate with an external device and receive electrical power through the first RDL structure, the second RDL structure, and the plurality of conductive vias of the interposer module, wherein:

the semiconductor device package comprises a plurality of bottom electronic devices including the bottom electronic device, and two or more of the bottom electronic devices are configured to communicate with each other via the double sided RDL structure, or
the semiconductor device package comprises a plurality of top electronic devices including the top electronic device, and two or more of the top electronic devices are configured to communicate with each other via the double sided RDL structure.

2. The semiconductor device package of claim 1 , further comprising:
a third RDL structure disposed below the bottom electronic device and below the interposer module,
the interposer module electrically connecting the double sided RDL structure to the third RDL structure.

3. The semiconductor device package of claim 2 , further comprising a conductive post electrically connecting the double sided RDL structure to the third RDL.

4. The semiconductor device package of claim 1 , wherein the double sided RDL structure electrically connects the active surface of the bottom electronic device to the interposer module.

5. The semiconductor device package of claim 1 , wherein the package body covers the back surface of the bottom electronic device.

6. The semiconductor device package of claim 1 , wherein the interposer component includes a routing layer electrically connecting a first one of the conductive vias to a second one of the conductive vias.

7. The semiconductor device package of claim 1 , wherein at least some traces of the first RDL structure are electrically connected to at least some traces of the second RDL structure.

8. The semiconductor device package of claim 2 , wherein the third RDL structure comprises a top RDL and a bottom RDL, and at least some traces of the top RDL are electrically connected to at least some traces of the bottom RDL.

9. The semiconductor device package of claim 1 , wherein the plurality of conductive vias includes a first conductive via having a smaller diameter for signal connection and a second conductive via having a larger diameter for power connection, ground connection, or combinations thereof.

10. The semiconductor device package of claim 1 , wherein a circumference of each of the conductive vias of the interposer module is circular in shape from a top view perspective.

11. A semiconductor device package comprising:
a top electronic device having an active surface;
a bottom electronic device having an active surface facing toward the active surface of the top electronic device, and a back surface opposite to the active surface of the bottom electronic device;
an interposer module including a plurality of conductive vias and having a top surface and a bottom surface, wherein the conductive vias of the interposer module have different diameters, wherein the top surface of the interposer module is not leveled with the active surface of the bottom electronic device, and wherein the bottom surface of the interposer module is not leveled with the back surface of the bottom electronic device;
a package body encapsulating the interposer module and the bottom electronic device and covering the back surface of the bottom electronic device, where the package body has a top surface and a bottom surface, wherein the top surface of the interposer module is leveled with the top surface of the package body, and wherein the bottom surface of the interposer module is leveled with the bottom surface of the package body; and
a double sided redistribution layer (RDL) structure disposed between the bottom electronic device and the top electronic device, the double sided RDL structure electrically connecting the active surface of the bottom electronic device to the active surface of the top electronic device, and electrically connected to the interposer module the double sided RDL comprising:
a first RDL structure,
a second RDL structure disposed over the first RDL structure and embedded under the top surface of the package body, and
a single dielectric layer between the active surface of the bottom electronic device and the active surface of the top electronic device, the single dielectric layer comprising a top surface exposing the first RDL structure and a bottom surface in direct contact with the second RDL structure, the bottom surface of the single dielectric layer being further in contact with the interposer module allowing the top electronic device and the bottom electronic device to communicate with an external device and receive electrical power through the first RDL structure, the second RDL structure, and the plurality of conductive vias of the interposer module, wherein:

the semiconductor device package comprises a plurality of bottom electronic devices including the bottom electronic device, and two or more of the bottom electronic devices are configured to communicate with each other via the double sided RDL structure, or
the semiconductor device package comprises a plurality of top electronic devices including the top electronic device, and two or more of the top electronic devices are configured to communicate with each other via the double sided RDL structure.

Assignees

• Advanced Semiconductor Eng

Inventors

• Chen William T
• Hunt John Richard
• Hung Chih-Pin
• Wang Chen-Chao
• Huang Chih-Yi

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title