Semiconductor device having stacked dies and stacked pillars and method of manufacturing thereof

Patent metadata

Field	Value
Publication number	US-10475770-B2
Application number	US-201715445568-A
Country	US
Kind code	B2
Filing date	Feb 28, 2017
Priority date	Feb 28, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

Various aspects of this disclosure provide a semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising a stacked die structure and a method of manufacturing thereof.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first substrate having no active electronic devices and comprising:
a first substrate top side;
a first substrate bottom side;
a first signal distribution layer; and
a first dielectric layer;

a first metal pillar on the first substrate top side;
a first semiconductor die comprising:
a first die bottom side comprising an active die side;
a first die top side; and
conductive bumps on the first die bottom side,
where the conductive bumps are coupled directly to the first substrate top side;

a second metal pillar above the first metal pillar, wherein a bottom end of the second metal pillar is connected to a top end of the first metal pillar;
a second semiconductor die comprising:
a second die top side comprising an active die side; and
a second die bottom side coupled to the first die top side, such that there is no intervening substrate between the first and second semiconductor dies;

a second substrate on a top end of the second metal pillar and on the second die top side; and
encapsulating material between the first substrate and the second substrate, wherein the encapsulating material encapsulates at least a lateral side of each of the first metal pillar, the first semiconductor die, the second metal pillar and the second semiconductor die, and the encapsulating material contacts and covers the first dielectric layer of the first substrate.

2. The semiconductor device of claim 1 , wherein the encapsulating material comprises:
a first encapsulating material comprising a top side that has a same height as the top end of the first metal pillar from the first substrate and that has a same height as the first die top side from the first substrate; and
a second encapsulating material comprising a bottom side that has a same height from the first substrate as the bottom end of the second metal pillar from the first substrate.

3. The semiconductor device of claim 2 , wherein:
the second encapsulating material does not cover the bottom side of the second semiconductor die;
the second semiconductor die comprises a second conductive bump having a top side that is at a same height from the first substrate as a top side of the second encapsulating material; and
a portion of the second die top side is covered by the second encapsulating material.

4. The semiconductor device of claim 2 , wherein:
the first die top side comprises an inactive die side; and
the second encapsulating material comprises only a single layer of a material and directly contacts and covers the first die top side.

5. The semiconductor device of claim 1 , comprising an adhesion member directly vertically between the second die bottom side and the first die top side, and wherein the conductive bumps of the first semiconductor die are soldered to the first substrate.

6. The semiconductor device of claim 5 , wherein the adhesion member is directly coupled to the second die bottom side, and the adhesion member does not contact the first die bottom side.

7. The semiconductor device of claim 6 , wherein the encapsulating material comprises:
a first encapsulating material comprising a top side that has a same height as the top end of the first metal pillar from the first substrate top side; and
a second encapsulating material that laterally surrounds the adhesion member, laterally surrounds the second semiconductor die, and covers at least a portion of the second die top side.

8. The semiconductor device of claim 7 , wherein:
a bottom side of the adhesion member has a same height from the top side of the first substrate as a bottom side of the second encapsulating material from the top side of the first substrate; and
the second encapsulating material contacts lands on the top side of the second semiconductor die.

9. The semiconductor device of claim 1 , wherein
the active die side of the first semiconductor die is electrically coupled to the active die side of the second semiconductor die through at least the first substrate, the first metal pillar, the second metal pillar, and the second substrate.

10. The semiconductor device of claim 1 , wherein:
the first metal pillar and the second metal pillar are displaced from each other in a direction perpendicular to a stacking direction in which the first metal pillar and the second metal pillar are stacked; and
the semiconductor device comprises a pillar redistribution structure comprising a conductive layer through which the first metal pillar and the second metal pillar are electrically connected;
the top end of the second metal pillar is coplanar with a conductive bump of the second semiconductor die; and
wherein the top end of the first metal pillar and the bottom end of the second metal pillar are vertically separated by only a thickness of the conductive layer of the pillar redistribution structure.

11. The semiconductor device of claim 10 , wherein the encapsulating material comprises:
a first encapsulating material comprising a top side that has a same height as the top end of the first metal pillar and as the top side of the first semiconductor die from the first substrate top side; and
a second encapsulating material between the first encapsulating material and the second substrate,
wherein the pillar redistribution structure is over the first encapsulating material and at least a portion of the pillar redistribution structure is embedded in the second encapsulating material.

12. The semiconductor device of claim 1 , wherein a center of the second semiconductor die is displaced from a center of the first semiconductor die in a direction perpendicular to a stacking direction in which the first semiconductor die and the second semiconductor die are stacked, and the second semiconductor die does not extend laterally beyond the lateral sides of the first semiconductor die; and
further comprising a third semiconductor die coupled to the first die top side such that there is no intervening substrate between the first and third semiconductor dies, wherein a first portion of the third semiconductor die is directly above the first semiconductor die and a second portion of the third semiconductor die is laterally displaced from the first semiconductor die.

13. The semiconductor device of claim 2 , comprising a conductive layer, and wherein:
the bottom end of the second metal pillar is connected to the top end of the first metal pillar through at least the conductive layer;
the conductive layer is positioned directly vertically between the first encapsulating material and the second encapsulating material, but not directly vertically between the first semiconductor die and the second semiconductor die; and
a bottom side of the conductive layer and the bottom side of the second encapsulating material are coplanar.

14. A semiconductor device comprising:
a first substrate;
a first metal pillar plated on a top side of the first substrate;
a first semiconductor die comprising:
a top side facing away from the first substrate; and
a bottom side facing the first substrate, and comprising pads that are connected to the top side of the first substrate with solder;

a second metal pillar plated above the first metal pillar, wherein a bottom end of the second metal pillar is connected to a top end of the first metal pillar;
a second semiconductor die comprising:
a top side facing away from the first semiconductor die and comprising pads; and
a bottom side coupled to the top side of the first semiconductor die, such that there is no intervening substrate between the first and second semiconductor dies;

a second sub

Assignees

• Amkor Technology Inc

Inventors

• Lee Won Geol
• Do Won Chul
• Yi Ji Hun

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title