Semiconductor package using a coreless signal distribution structure

Patent metadata

Field	Value
Publication number	US-2016233196-A1
Application number	US-201615018668-A
Country	US
Kind code	A1
Filing date	Feb 8, 2016
Priority date	Feb 9, 2015
Publication date	Aug 11, 2016
Grant date	—

Abstract

A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a coreless signal distribution structure comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface; a first semiconductor die having a first bond pad on a first die surface, the first semiconductor die bonded to the first surface of the coreless signal distribution structure via the first bond pad; a second semiconductor die having a second bond pad on a second die surface, the second semiconductor die bonded to the second surface of the coreless signal distribution structure via the second bond pad; a metal post electrically coupled to the first surface of the coreless signal distribution structure; and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the coreless signal distribution structure.

2 . The semiconductor device according to claim 1 , wherein the metal post comprises copper and extends through the encapsulant material.

3 . The semiconductor device according to claim 1 , comprising a second encapsulant material encapsulating the second semiconductor die.

4 . The semiconductor device according to claim 3 , comprising a second metal post coupled to the coreless signal distribution structure and extending through the second encapsulant material.

5 . The semiconductor device according to claim 3 , wherein a surface of the second encapsulant is coplanar with a surface of the second semiconductor die opposite the second die surface.

6 . The semiconductor device according to claim 1 , wherein a conductive pillar electrically couples the first bond pad of the first semiconductor die to the coreless signal distribution structure.

7 . The semiconductor device according to claim 1 , comprising a redistribution structure on the first encapsulant and electrically coupled to the metal post, wherein the redistribution structure comprises at least one conductive layer and at least one dielectric layer.

8 . The semiconductor device according to claim 1 , wherein the coreless signal distribution structure has a linewidth of 1-10 μm.

9 . A semiconductor device comprising:
a coreless signal distribution structure comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface; a first semiconductor die having a first bond pad on a first die surface, the first semiconductor die bonded to the first surface of the coreless signal distribution structure via the first bond pad; a second semiconductor die having a second bond pad on a second die surface, the second semiconductor die bonded to the second surface of the coreless signal distribution structure via the second bond pad; a first encapsulant material encapsulating side surfaces of the first semiconductor die and a portion of the first surface of the coreless signal distribution structure; and a redistribution structure on the first encapsulant, wherein the redistribution structure comprises at least one conductive layer and at least one dielectric layer.

10 . The semiconductor device of claim 9 , comprising a first metal post on the coreless signal distribution structure adjacent to a first edge of the first semiconductor die, the first metal post extending through the encapsulant material.

11 . The semiconductor device of claim 10 , comprising a second metal post on the coreless signal distribution structure adjacent to a second edge of the first semiconductor die, the second metal post extending through the encapsulant material.

12 . The semiconductor device of claim 11 , wherein the redistribution structure is electrically coupled to the first metal post and an interconnection structure on the first encapsulant.

13 . The semiconductor device of claim 12 , wherein a dielectric layer of the redistribution structure contacts the first metal post and the interconnection structure but not the second metal post.

14 . The semiconductor device of claim 12 , wherein the interconnection structure comprises a conductive bump.

15 . The semiconductor device of claim 9 , comprising encapsulating the second semiconductor die utilizing a second encapsulant material.

16 . The semiconductor device of claim 11 , wherein a second encapsulant encapsulates the second semiconductor die and is coplanar with a surface of the second semiconductor die opposite the second die surface.

17 . A method of fabricating a semiconductor device, the method comprising:
fabricating a coreless signal distribution structure by forming at least one dielectric layer and at least one conductive layer on a first temporary substrate; forming a metal post on the coreless signal distribution structure; bonding a first semiconductor die to a first surface of the coreless signal distribution structure; encapsulating the first semiconductor die, the metal post, and a portion of the first surface of the coreless signal distribution structure utilizing an encapsulant material; forming a redistribution structure on the encapsulant material; bonding a second substrate to the redistribution structure; removing the first temporary substrate; and bonding a second semiconductor die to a second surface of the signal distribution structure opposite the first surface.

18 . The method of claim 17 , comprising encapsulating the second semiconductor die utilizing a second encapsulant material.

19 . The method of claim 18 , wherein a surface of the second encapsulant material is coplanar with a surface of the second semiconductor die.

20 . The method of claim 17 , comprising forming a conductive bump on the post coplanar with the redistribution structure.

Assignees

• Amkor Technology Inc

Inventors

• Kim Do Hyung
• Park Jung Soo
• Han Seung Chul

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W46/401

  for identification or tracking · CPC title