Insulating gate separation structure for transistor devices

Patent metadata

Field	Value
Publication number	US-10879073-B2
Application number	US-201916679829-A
Country	US
Kind code	B2
Filing date	Nov 11, 2019
Priority date	Oct 30, 2018
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

One integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, wherein the first and second transistor devices have a gate width that extends in a gate width direction and a gate length that extends in a gate length direction, and a gate separation structure positioned between the first and second final gate structures, the gate separation structure comprising at least one insulating material. The gate separation structure further has a substantially uniform width in the gate width direction for substantially an entire vertical height of the gate separation structure and a first side surface and a second side surface, wherein an end surface of the first final gate structure contacts the first side surface and an end surface of the second final gate structure contacts the second side surface.

First claim

What is claimed:

1. An integrated circuit product, comprising:
a first final gate structure for a first transistor device;
a second final gate structure for a second transistor device, wherein said first and second transistor devices have a gate width that extends in a gate width direction and a gate length that extends in a gate length direction; and
a gate separation structure positioned between said first and said second final gate structures, said gate separation structure comprising at least one insulating material, said gate separation structure further comprising:
a substantially uniform width in said gate width direction for substantially an entire vertical height of said gate separation structure; and
a first side surface and a second side surface, said second side surface being opposite to said first side surface, wherein an end surface of said first final gate structure contacts said first side surface of said gate separation structure and an end surface of said second final gate structure contacts said second side surface of said gate separation structure.

2. The integrated circuit product of claim 1 :
wherein said end surface of said first final gate structure comprises a first high-k (k value of 10 or greater) gate insulation layer, wherein a first contact area between said first high-k gate insulation layer and said first side surface is a generally U-shaped contact area; and
wherein said end surface of said second final gate structure comprises a second high-k (k value of 10 or greater) gate insulation layer, wherein a second contact area between said second high-k gate insulation layer and said second side surface is a generally U-shaped contact area.

3. The integrated circuit product of claim 1 , further comprising:
source/drain regions for said first and second transistor devices;
a conductive source/drain structure that is conductively coupled to a source/drain region of said first transistor device and conductively coupled to a source/drain region of said second transistor device; and
a conductive source/drain metallization cap structure positioned on and in contact with an upper surface of said conductive source/drain structure, wherein said conductive source/drain metallization cap structure comprises a material that is different than a material of said conductive source/drain structure, and wherein an upper surface of a first gate cap for said first final gate structure and an upper surface of a second gate cap of said second final gate structure is substantially free of the material of said conductive source/drain metallization cap structure.

4. The integrated circuit product of claim 1 , further comprising:
a first gate cap positioned above said first final gate structure, said first gate cap having an upper surface; and
a second gate cap positioned above said second final gate structure, said second gate cap having an upper surface, wherein an upper surface of said gate separation structure is substantially coplanar with said upper surfaces of said first and second gate caps.

5. The integrated circuit product of claim 1 , further comprising a sidewall spacer positioned adjacent sidewall surfaces of said first final gate structure and said second final gate structure, wherein said gate separation structure contacts an internal surface of said sidewall spacer.

6. The integrated circuit product of claim 1 , wherein said gate separation structure comprises at least two different insulating materials.

7. The integrated circuit product of claim 2 , wherein said first high-k gate insulation layer and said second high-k gate insulation layer comprise a same material.

8. The integrated circuit product of claim 1 , wherein said first final gate structure comprises a high-k (k value of 10 or greater) gate insulation layer and a gate electrode, said gate electrode comprising at least one metal-containing layer of material, said at least one insulating material comprising silicon nitride, silicon dioxide, a mixture of two or more materials of silicon oxide, silicon nitride and silicon carbide, or a low-k insulating material (k value of 3.3, or less), and said first and second transistor devices are FinFET devices.

9. The integrated circuit product of claim 3 , wherein said conductive source/drain structure comprises one of tungsten, a metal, a metal compound, a metal silicide, cobalt silicide or nickel silicide, titanium silicide, or nickel platinum silicide, and said conductive source/drain metallization cap structure comprises one of ruthenium, iridium, ruthenium oxide, iridium oxide, platinum, a metal-containing material or a metal compound.

10. An integrated circuit product, comprising:
a first final gate structure for a first transistor device, wherein said first final gate structure comprises a first high-k (k value of 10 or greater) gate insulation layer;
a second final gate structure for a second transistor device, wherein said second final gate structure comprises a second high-k (k value of 10 or greater) gate insulation layer and wherein said first and second transistor devices have a gate width that extends in a gate width direction and a gate length that extends in a gate length direction; and
a gate separation structure positioned between said first and said second final gate structures, said gate separation structure comprising at least one insulating material, a first side surface and a second side surface, said second side surface being opposite to said first side surface, wherein an end surface of said first final gate structure contacts said first side surface of said gate separation structure and an end surface of said second final gate structure contacts said second side surface of said gate separation structure and wherein a first contact area between said first high-k gate insulation layer and said first side surface is a generally U-shaped contact area and a second contact area between said second high-k gate insulation layer and said second side surface is a generally U-shaped contact area.

11. The integrated circuit product of claim 10 , further comprising:
source/drain regions for said first and second transistor devices;
a conductive source/drain structure that is conductively coupled to a source/drain region of said first transistor device and conductively coupled to a source/drain region of said second transistor device; and
a conductive source/drain metallization cap structure positioned on and in contact with an upper surface of said conductive source/drain structure, wherein said conductive source/drain metallization cap structure comprises a material that is different than a material of said conductive source/drain structure, and wherein an upper surface of a first gate cap for said first final gate structure and an upper surface of a second gate cap for said second final gate structure is substantially free of said material of said conductive source/drain metallization cap structure.

12. The integrated circuit product of claim 10 , further comprising:
a first gate cap positioned above said first final gate structure, said first gate cap having an upper surface; and
a second gate cap positioned above said second final gate structure, said second gate cap having an upper surface, wherein an upper surface of said gate separation structure is substantially coplanar with said upper surfaces of said first and second gate caps.

13. The integrated circuit product of claim 10 , further comprising a sidewall spacer positioned adjacent sidewall surfaces of said first final gate structure and said second final gate structure, wherein said gate separation structure contacts an internal surface of said side

Assignees

• Globalfoundries Inc

Inventors

• Park Chanro
• Xie Ruilong
• Zang Hui
• Economikos Laertis
• Labonte Andre

Classifications

• H10P50/267

  using plasmas · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title