Superconducting non-destructive readout circuits

Patent metadata

Field	Value
Publication number	US-10868540-B2
Application number	US-201916700615-A
Country	US
Kind code	B2
Filing date	Dec 2, 2019
Priority date	Jul 31, 2018
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.

First claim

What is claimed is:

1. A reciprocal quantum logic (RQL) demultiplexer circuit comprising:
respective ports for a selector input, a data input, a first output, and a second output;
a selector Josephson junction connected between a first node and a circuit ground and configured to trigger upon assertion of a selector input signal from the selector input port;
first and second circuit branches diverging from the first node and converging at a second node, the second node being configured to receive the data input at the data input port;
wherein the RQL demultiplexer circuit is configured such that non-assertion or assertion of the selector signal respectively selects between:
a signal arriving on the data input port being propagated through the first circuit branch to the first output port, or
the signal arriving on the data input port being propagated through the second circuit branch to the second output port.

2. The RQL demultiplexer circuit of claim 1 , wherein the first circuit branch comprises:
a first inductor connected between the first node and a third node;
a pulse generator connected to the third node, the pulse generator comprising two Josephson junctions and an AC bias source;
an escape Josephson junction connected between the third node and a fourth node; and
a first output Josephson junction connected between the fourth node and the circuit ground.

3. The RQL demultiplexer circuit of claim 1 , wherein the second circuit branch comprises:
a second inductor connected between the first node and a fifth node;
a second output Josephson junction connected between a sixth node and the circuit ground; and
a third output Josephson junction connected between the fifth node and the circuit ground.

4. The RQL demultiplexer circuit of claim 1 , wherein:
the first circuit branch comprises:
a first inductor connected between the first node and a third node;
a pulse generator connected to the third node, the pulse generator comprising two Josephson junctions and an AC bias source;
an escape Josephson junction connected between the third node and a fourth node; and
a first output Josephson junction connected between the fourth node and the circuit ground; and

the second circuit branch comprises:
a second inductor connected between the first node and a fifth node;
a second output Josephson junction connected between a sixth node and the circuit ground; and
a third output Josephson junction connected between the fifth node and the circuit ground.

5. The RQL demultiplexer circuit of claim 4 , wherein the demultiplexer circuit is configured such that non-assertion or assertion of the selector signal respectively selects between:
a signal arriving on the data input port being propagated through the fourth node to the first output port, or
the signal arriving on the data input port being propagated through the sixth and fifth nodes to the second output port.

6. The RQL demultiplexer circuit of claim 4 , further comprising:
a third inductor connected between the second node and the fourth node in the first circuit branch;
a fourth inductor connected between the second node and the sixth node in the second circuit branch; and
a fifth inductor connected between the sixth node and the fifth node in the second circuit branch.

7. The RQL demultiplexer circuit of claim 1 , further comprising a Josephson transmission line (JTL) between the data input port and the second node.

8. The RQL demultiplexer circuit of claim 1 , having no more than twelve inductors, exclusive of any inductors in input or output Josephson transmission lines (JTLs).

9. The RQL demultiplexer circuit of claim 1 , having no more than seven Josephson junctions, exclusive of any Josephson junctions in input or output Josephson transmission lines (JTLs).

10. The RQL demultiplexer circuit of claim 1 , having no more than seven Josephson junctions and no more than twelve inductors, exclusive of any Josephson junctions or inductors in input or output Josephson transmission lines (JTLs).

Assignees

• Herr Anna Y
• Herr Quentin P
• Clarke Ryan Edward
• Hearne Iii Harold Clifton
• Braun Alexander Louis
• Burnett Randall M
• Lee Timothy Chi Chao
• Northrop Grumman Systems Corp

Inventors

• Herr Anna Y
• Herr Quentin P
• Clarke Ryan Edward
• Hearne Iii Harold Clifton
• Braun Alexander Louis
• Burnett Randall M
• Lee Timothy Chi-Chao

Classifications

• H03K19/195 Primary

  using superconductive devices · CPC title

• H03K3/38

  by the use, as active elements, of superconductive devices · CPC title

• G11C11/44 Primary

  using super-conductive elements, e.g. cryotron · CPC title

• G11C8/16

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title

• G06N10/00

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title