Superconductive gate system

Patent metadata

Field	Value
Publication number	US-2016013791-A1
Application number	US-201414325518-A
Country	US
Kind code	A1
Filing date	Jul 8, 2014
Priority date	Jul 8, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

One embodiment includes a superconductive gate system. The superconductive gate system includes a Josephson D-gate circuit comprising a bi-stable loop configured to store a digital state as one of a first data state and a second data state in response to an enable single flux quantum (SFQ) pulse provided on an enable input and a respective presence of or absence of a data SFQ pulse provided on a data input. The digital state can be provided at an output. The readout circuit is coupled to the output and can be configured to reproduce the digital state as an output signal.

First claim

What is claimed is:

1 . A superconductive gate system comprising:
a Josephson D-gate circuit comprising a bi-stable loop configured to store a digital state as one of a first data state and a second data state in response to an enable single flux quantum (SFQ) pulse provided on an enable input and a respective presence of or absence of a data SFQ pulse provided on a data input, the digital state being provided at an output; and a readout circuit coupled to the output and being configured to reproduce the digital state as an output signal.

2 . The system of claim 1 , wherein the bi-stable loop comprises a first Josephson junction associated with the enable input and a second Josephson junction associated with the data input, wherein the digital state corresponds to a superconducting phase associated with the first Josephson junction.

3 . The system of claim 2 , wherein the Josephson D-gate circuit further comprises:
a third Josephson junction interconnecting the enable input and the first Josephson junction, wherein the output is coupled to a node interconnecting the first and third Josephson junctions; a fourth Josephson junction interconnecting the data input and the second Josephson junction; a first bias transistor interconnecting the first and second Josephson junctions and being configured to induce a bias in the bi-stable loop in response to a bias current; and a second bias transistor coupled to a node interconnecting the second and fourth Josephson junctions and being configured to induce a bias in the fourth Josephson junction in response to the bias current.

4 . The system of claim 2 , wherein the Josephson D-gate circuit further comprises:
a third Josephson junction interconnecting the enable input and the first Josephson junction, wherein the output is coupled to a node interconnecting the first and third Josephson junctions; an inductor interconnecting the data input and the second Josephson junction; a bias transistor interconnecting the first and second Josephson junctions and being configured to induce a bias in the bi-stable loop in response to a bias current.

5 . The system of claim 1 , wherein the bi-stable loop comprises a plurality of the Josephson junctions and is configured to conduct a bi-stable current in a first direction that is indicative of the first data state and in a second direction that is indicative of the second data state, wherein at least a portion of the plurality of the Josephson junctions are configured to sequentially trigger in response to the data on the enable input and the data input to set the direction of the bi-stable current between the first direction and the second direction during a write operation.

6 . The system of claim 1 , wherein the Josephson D-gate circuit is configured to set a bi-stable current in the bi-stable loop in a first direction in response to the enable SFQ pulse and the absence of the data SFQ pulse to store the first data state, and to set the bi-stable current in the bi-stable loop in a second direction opposite the first direction in response to the enable SFQ pulse and the presence of the data SFQ pulse to store the second data state.

7 . The system of claim 6 , wherein the Josephson D-gate circuit is configured to maintain the stored digital state in response to an absence of the enable SFQ pulse.

8 . The system of claim 6 , wherein the Josephson D-gate circuit is configured to store the second data state in response to the data SFQ pulse being time-delayed relative to the enable SFQ pulse.

9 . The system of claim 8 , wherein the Josephson D-gate circuit comprises a reciprocal quantum logic (RQL) bias architecture, wherein the time-delay comprises a positive SFQ pulse provided on the data input precedes a negative SFQ pulse provided on the enable input.

10 . A memory cell comprising the superconductive gate system of claim 1 , the memory cell further comprising:
a first interconnect that couples the enable input to a word-line and is configured to provide the enable SFQ pulse based on a word-write signal that propagates on the word-line; and a second interconnect that couples the data input to a bit-line and is configured to provide the data SFQ pulse based on a bit-write signal that propagates on the bit-line.

11 . The memory cell of claim 10 , wherein the word-write signal and the bit-write signal are each configured as digital signals, wherein the first interconnect is configured as a passive interconnect to provide the enable SFQ pulse in response to a first binary state of the word-write signal, and wherein the second interconnect is configured as a passive interconnect to provide the data SFQ pulse in response to a first binary state of the bit-write signal.

12 . A superconductive memory system comprising a plurality of memory cells of claim 10 arranged in an array of at least one row and at least one column, wherein the word-line is one of a respective at least one word-line configured to provide one of a respective at least one word-write signal to select a respective one of the at least one row during a data write operation, and wherein the bit-line is one of a respective at least one bit-line configured to provide one of a respective at least one bit-write signal to write the digital state into the bi-stable loop associated with each memory cell of the respective selected one of the at least one row.

13 . A method for writing a digital state into a memory cell, the method comprising:
generating an enable single flux quantum (SFQ) pulse to enable a write operation to the memory cell; providing an enable SFQ pulse on an enable input of a Josephson D-gate circuit associated with the memory cell, the Josephson D-gate circuit comprising a bi-stable loop having a bi-stable current; and either providing a data SFQ pulse on a data input of the Josephson D-gate circuit to set the bi-stable current in a first direction associated with a first data state in response to the enable SFQ pulse, or not providing the data SFQ pulse on the data input of the Josephson D-gate circuit to set the bi-stable current in a second direction opposite the first direction associated with a second data state in response to the enable SFQ pulse.

14 . The method of claim 13 , wherein providing the data SFQ pulse comprises providing the data SFQ pulse on the data input to sequentially trigger a first portion of a plurality of the Josephson junctions in response to the data SFQ pulse and the enable SFQ pulse to set the bi-stable current in the first direction indicative of the first data state, and wherein providing no data SFQ pulse comprises providing no SFQ pulse to sequentially trigger a second portion of the plurality of the Josephson junctions in response to the enable SFQ pulse to set the bi-stable current in the second direction indicative of the second data state.

15 . The method of claim 13 , wherein providing the data SFQ pulse comprises providing the data SFQ pulse in a time-delay manner with respect to the enable SFQ pulse, such that a positive data SFQ pulse precedes a negative enable SFQ pulse.

16 . The method of claim 13 , wherein generating the enable SFQ pulse comprises providing the enable SFQ pulse to enable a write operation to each of the memory cell and a plurality of additional memory cells in a row that are coupled to a word-line, and wherein providing the data SFQ pulse and providing no data SFQ pulse comprises providing one of the data SFQ pulse and no data SFQ pulse to each of the memory cell and a plurality of additional memory cells in a column that are coupled to a bit-line to set

Assignees

• Herr Anna Y
• Herr Quentin P
• Northrop Grumman Systems Corp

Inventors

• Herr Anna Y
• Herr Quentin P

Classifications

• H03K19/1952

  with electro-magnetic coupling of the control current · CPC title

• H03K19/0008 Primary

  Arrangements for reducing power consumption · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• G11C11/44 Primary

  using super-conductive elements, e.g. cryotron · CPC title

• H03K3/38

  by the use, as active elements, of superconductive devices · CPC title