Wave-pipelined logic circuit scanning system

Patent metadata

Field	Value
Publication number	US-9864005-B1
Application number	US-201615253544-A
Country	US
Kind code	B1
Filing date	Aug 31, 2016
Priority date	Aug 31, 2016
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

One example embodiment includes a circuit system. The system includes a wave-pipelined combinational logic circuit comprising at least one logic gate between an input node and at least one output node and configured to perform logic operations on a data sequence received at the input node. The system also includes a scan path connected to the input node and comprising at least one delay element configured to propagate the data sequence from the input to a scan path output to capture values of the data sequence provided to the wave-pipelined combinational logic circuit as a serial data stream. The system also includes a scan point device configured to deliver one of input data and scan data as the data sequence to the wave-pipelined combinational logic circuit and to the scan path via the input node in a respective one of a normal operating mode and a scan mode.

First claim

What is claimed is:

1. A circuit system comprising:
a wave-pipelined combinational logic circuit comprising at least one logic gate between an input node and at least one output node and configured to perform logic operations on a data sequence received at the input node;
a scan path connected to the input node and comprising at least one delay element configured to propagate the data sequence from the input to a scan path output to capture values of the data sequence provided to the wave-pipelined combinational logic circuit as a serial data stream; and
a scan point device configured to deliver one of input data and scan data as the data sequence to the wave-pipelined combinational logic circuit and to the scan path via the input node in a respective one of a normal operating mode and a scan mode.

2. The system of claim 1 , wherein the scan path is a first scan path of a plurality of scan paths connected to respective inputs of the wave-pipelined combinational logic circuit, each of the plurality of scan paths comprising at least one delay element, and wherein the scan point device is a plurality of a scan point devices interconnecting the plurality of scan paths with the wave-pipelined combinational logic circuit, such that the plurality of scan paths are arranged in series in the scan mode via each of the respective plurality of scan point devices to form a scan chain through which the serial data stream is propagated between a system scan input and a system scan output associated with the circuit system to capture the values of the data sequence provided to the wave-pipelined combinational logic circuit.

3. The system of claim 2 , wherein each of the plurality of scan paths comprises a plurality of delay elements sufficient in number that is greater than or equal to a largest number of pipeline stages from the input node to one of the at least one output node.

4. The system of claim 2 , wherein each of the plurality of scan point devices comprises a multiplexer comprising a first input connected to an output of the wave-pipelined combinational logic circuit and configured to receive the input data and a second input connected to a respective scan path output of one of the plurality of scan paths and configured to receive the scan data, the multiplexer being configured to provide the data sequence as the input data in the normal operating mode and to provide the data sequence as the scan data in the scan mode based on a value of a mode signal.

5. The system of claim 2 , wherein each of the at least one delay element in each of the plurality of scan paths has an associated delay of approximately one clock-cycle of a clock signal, such that each of the plurality of scan paths is configured to capture the values of each of the respective data sequences provided to each of a respective plurality of inputs to the wave-pipelined combinational logic circuit at a given clock-cycle.

6. The system of claim 2 , wherein the clock signal is provided continuously to the circuit system, such that the circuit system is configured to toggle between the normal operating mode and the scan mode without interruption of the clock signal to provide a scan of the circuit system at full speed.

7. The system of claim 2 , wherein the serial data stream is output from the system scan output to a logic monitoring system configured to evaluate the serial data stream, wherein the system scan input is configured to receive the serial data stream provided from the logic monitoring system to restore the values of the data sequence provided to each of the respective plurality of inputs of the wave-pipelined combinational logic circuit at the given clock-cycle.

8. The system of claim 7 , wherein the logic monitoring system is configured to provide a mode signal that is provided to each of the plurality of scan point devices, wherein the logic monitoring system is configured to facilitate a logic test by switching the circuit system from the scan mode to the normal operating mode via the mode signal for at least one clock-cycle in response to the values of the data sequence provided to the wave-pipelined combinational logic circuit being restored and by subsequently switching the circuit system from the normal operating mode to the scan mode via the mode signal to provide the serial data steam back to the logic monitoring system to capture the values of the data sequence provided to the wave-pipelined combinational logic circuit after operation of the wave-pipelined combinational logic circuit for the at least one clock-cycle.

9. The system of claim 7 , wherein the logic monitoring system is configured to generate a predetermined serial test stream that is provided to the system scan input to provide the predetermined serial test stream as the data sequence to the wave-pipelined combinational logic circuit during the scan mode.

10. The system of claim 2 , wherein the circuit system comprises at least one internal memory device that is disabled during the scan mode via the mode signal.

11. The system of claim 1 , wherein the circuit system is configured as a Reciprocal Quantum Logic (RQL) circuit.

12. A computer readable medium that, when executed, is configured to implement a method for monitoring data in a circuit system, the method comprising:
providing each of a plurality of data sequences to a respective one of a plurality of scan paths and a respective plurality of inputs of a wave-pipelined combinational logic circuit via a respective plurality of scan point devices, the wave-pipelined combinational logic circuit comprising at least one logic gate between an input node and at least one output node and configured to perform logic operations on a data sequence received at the input node;
performing logic operations on each of the plurality of data sequences via the;
switching each of the plurality of scan point devices from a normal operating mode to a scan mode in response to a mode signal;
propagating a serial data stream corresponding to the plurality of data sequences through each of the plurality of scan paths via each of the respective plurality of scan point devices and from a system scan output of the circuit system; and
analyzing values of the plurality of data sequences at a given clock-cycle of a clock signal based on the serial data stream via a logic monitoring system connected to the scan output.

13. The medium of claim 12 , further comprising providing the serial data stream from the logic monitoring system to a system scan input of the circuit system to restore values of the plurality of data sequences to the values of the plurality of data sequences at the given clock-cycle.

14. The medium of claim 13 , further comprising:
switching each of the plurality of scan point devices from the scan mode to the normal operating mode in response to the mode signal;
switching each of the plurality of scan point devices from the normal operating mode to the scan mode in response to the mode signal after at least one subsequent clock-cycle of the clock signal;
propagating the serial data stream through each of the plurality of scan paths via each of the respective plurality of scan point devices and from the scan output of the circuit system based on the clock signal; and
analyzing the values of the data sequence associated with the wave-pipelined combinational logic circuit via the logic monitoring system.

15. The medium of claim 12 , further comprising:
disabling memory associated with the circuit system in the scan mode;
generating a predetermined serial test stream, at least a portion of the predetermined serial test stream corresponding to

Assignees

• Carmean Douglas
• Smith Burton J
• Northrop Grumman Systems Corp

Inventors

• Carmean Douglas
• Smith Burton J

Classifications

• G01R31/318544

  Scanning methods, algorithms and patterns (G01R31/3183 takes precedence) · CPC title

• H03K3/38 Primary

  by the use, as active elements, of superconductive devices · CPC title

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• G01R31/318572

  Input/Output interfaces · CPC title

• H03K5/19

  Monitoring patterns of pulse trains (indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02) · CPC title