Power reduction in an array of data processing engines
US-12554310-B2 · Feb 17, 2026 · US
This page is not indexed by search engines while we improve data quality.
Tuan Tim patents
Tuan Tim is listed as an inventor on 38 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Tuan Tim |
| Total patents | 38 |
| First publication | Apr 21, 2015 |
| Latest publication | Feb 17, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Decoupling processing and interface clocks in an ipu
US-2025370949-A1 · Dec 4, 2025 · US
Multiple partitions in a data processing array
US-2025343549-A1 · Nov 6, 2025 · US
Multiple partitions in a data processing array
US-12401364-B2 · Aug 26, 2025 · US
Controller for an array of data processing engines
US-2025208907-A1 · Jun 26, 2025 · US
Integrating an ai accelerator with a cpu on a soc
US-2025209036-A1 · Jun 26, 2025 · US
Power domains in a system on a chip
US-2025208682-A1 · Jun 26, 2025 · US
Power reduction in an array of data processing engines
US-2025208687-A1 · Jun 26, 2025 · US
Data processing array interface having interface tiles with multiple direct memory access circuits
US-12164451-B2 · Dec 10, 2024 · US
Multi-die integrated circuit with data processing engine array
US-12001367-B2 · Jun 4, 2024 · US
Recent patents
Latest publications not already listed above.
Data processing engine arrangement in a device
US-11972132-B2 · Apr 30, 2024 · US
Multiple partitions in a data processing array
US-2024088900-A1 · Mar 14, 2024 · US
Multiple partitions in a data processing array
US-11848670-B2 · Dec 19, 2023 · US
Data processing array interface having interface tiles with multiple direct memory access circuits
US-2023376437-A1 · Nov 23, 2023 · US
Multiple partitions in a data processing array
US-2023336179-A1 · Oct 19, 2023 · US
Multi-die integrated circuit with data processing engine array
US-2023289311-A1 · Sep 14, 2023 · US
Multi-die integrated circuit with data processing engine array
US-11693808-B2 · Jul 4, 2023 · US
Multi-addressing mode for DMA and non-sequential read and write patterns
US-11669464-B1 · Jun 6, 2023 · US
Data processing engine arrangement in a device
US-2023131698-A1 · Apr 27, 2023 · US
Learning-based power modeling of a processor core and systems with multiple processor cores
US-2023044581-A1 · Feb 9, 2023 · US
Memory tiles in data processing engine array
US-11520717-B1 · Dec 6, 2022 · US
Data processing engines with cascade connected cores
US-11443091-B1 · Sep 13, 2022 · US
Programmable device having a data processing engine (DPE) array
US-11386020-B1 · Jul 12, 2022 · US
Multi-die integrated circuit with data processing engine array
US-2022197846-A1 · Jun 23, 2022 · US
Data processing engine array architecture with memory tiles
US-11336287-B1 · May 17, 2022 · US
Multi-port stream switch for stream interconnect network
US-11323391-B1 · May 3, 2022 · US
Multi-die integrated circuit with data processing engine array
US-2022100691-A1 · Mar 31, 2022 · US
Multi-die integrated circuit with data processing engine array
US-11288222-B1 · Mar 29, 2022 · US
Activity-aware clock gating for switches
US-11223351-B1 · Jan 11, 2022 · US
Data processing engine arrangement in a device
US-10866753-B2 · Dec 15, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Xilinx Inc | 38 |
| Advanced Micro Devices Inc | 5 |
| Tuan Tim | 4 |
| Mohan Sundararajarao | 1 |
| Chung Daniel | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F15/7807 | 15 |
| G06F15/7825 | 14 |
| Y02D10/00 | 12 |
| G06F15/7867 | 9 |
| G06F13/1668 | 8 |