Processing system with interspersed processors with multi-layer interconnection

Patent metadata

Field	Value
Publication number	US-9990241-B2
Application number	US-201715631925-A
Country	US
Kind code	B2
Filing date	Jun 23, 2017
Priority date	Nov 21, 2012
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of processors;
a plurality of configurable communication elements coupled to the plurality of processors in an interspersed arrangement;
wherein a particular configurable communication element of the plurality of configurable communication elements is coupled to a first subset of the plurality of processors, and to a second subset of the plurality of processors different from the first subset; and
wherein the particular configurable communication element is configured to receive one or more messages from a particular processor included in the first or second subset of the plurality of processors, and forward the one or more messages to another configurable communication element of the plurality of configurable communication elements using configuration information; and
wherein one or more configurable communication elements of the plurality of configurable communication elements are interspersed between the another configurable communication element and the particular configurable communication element.

2. The apparatus of claim 1 , wherein the one or more messages includes a request for access to a particular resource, and wherein the particular configurable communication element of the plurality of configurable communication elements is further configured to arbitrate between multiple requests for access to the particular resource.

3. The apparatus of claim 1 , wherein the particular configurable communication element is further configured to forward the one or more messages to the another configurable communication element based upon an amount of message traffic to the another configurable communication element.

4. The apparatus of claim 1 , wherein the particular configurable communication element of the plurality of configurable communication elements is further configured to receive the configuration information via a serial bus.

5. The apparatus of claim 1 , wherein the particular configurable communication element of the plurality of configurable communication elements includes a register configured to store at least a portion of the configuration information.

6. The apparatus of claim 1 , wherein the particular configurable communication element is further configured to forward a particular message of the one or more messages to the another configurable communication element based upon header information included the particular message.

7. A method of operating a multiprocessors system, comprising:
designating a first subset of a plurality of processors for receiving a first plurality of messages from a particular configurable communication element of a plurality of configurable communication elements, wherein the plurality of configurable communication elements is coupled to the plurality of processors in an interspersed arrangement;
designating a second subset of the plurality of processors for receiving a second plurality of messages from the particular configurable communication element, wherein the second subset is different than the first subset;
receiving, by the particular configurable communication element, a message from a particular processor included in the first or second subset of the plurality of processors; and
forwarding the message to another configurable communication element of the plurality of configurable communication elements using configuration information; and
wherein one or more configurable communication elements of the plurality of configurable communication elements are interspersed between the another configurable communication element and the particular configurable communication element.

8. The method of claim 7 , further comprising forwarding the message to the another configurable communication element based upon an amount of message traffic to the another configurable communication element.

9. The method of claim 8 , further comprising, monitoring the amount of message traffic by the particular configurable communication element.

10. The method of claim 7 , further comprising receiving, by the particular configurable communication element, the configuration information via a serial bus.

11. The method of claim 7 , storing at least a portion of the configuration information in a register included in the particular configurable communication element.

12. The method of claim 7 , further comprising forwarding the message to the another configurable communication element based upon header information include in the message.

13. The method of claim 7 , further comprising deactivating a channel from the particular configurable communication element to the another configurable communication element in response to determining the message has been transmitted.

14. The method of claim 13 , wherein deactivating the channel includes detecting a particular code included in the message.

15. A system, comprising:
a plurality of processors,
a plurality of memories interspersed among the plurality of processors, wherein each memory is coupled to a subset of the plurality of processors; and
a plurality of routing engines, wherein each routing engine of the plurality of routing engines is coupled to a respective one of the plurality of memories, a first subset of a plurality of links, and a second subset of the plurality of links;
wherein each link of the first subset of the plurality of links is coupled to a respective one of a first subset of the plurality of routing engines;
wherein each link of the second subset of the plurality of links is coupled to a respective one of a second subset of the plurality of routing engines;
wherein a particular routing engine included of the plurality of routing engines is coupled to first subset of the plurality of processors, and to a second subset of the plurality of processors different from the first subset, and wherein a particular processor included in the second subset of the plurality of processor is not physically adjacent to the particular routing engine; and
wherein the particular routing engine is configured to:
receive one or more messages from a particular processor included in the first or second subset of the plurality of processors; and
forward the one or more messages to another routing engine of the plurality of routing engines using configuration information,

wherein one or more routing engines of the plurality of routing engines are interspersed between the another routing engine and the particular routing engine.

16. The system of claim 15 , wherein the one or more messages includes a request for access to a particular resource, and wherein the particular routing engine of the plurality of routing engines is further configured to arbitrate between multiple requests for access to the particular resource.

17. The system of claim 15 , wherein particular routing engine is further configured to forward the one or more messages to the another routing engine based upon an amount of message traffic to the another routing engine.

18. The system of claim 15 , wherein the particular routing engine of the plurality of routing engines is further configured to receive the configuration information via a serial bus.

19. The system of claim 15 , wherein the particular routing engine of the plurality of routing engines includes a register configured to store at least a portion of the configuration information.

20. The system of claim 15 , wherein the particular routing engine is further configured to forward a particular message of the one or more messages to the another rout

Assignees

• Coherent Logix Inc

Inventors

• Dobbs Carl S
• Trocino Michael R
• Solka Michael B

Classifications

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F15/8038

  Associative processors · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F9/546 Primary

  Message passing systems or structures, e.g. queues · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title