Three-dimensional memory device having a slimmed aluminum oxide blocking dielectric and method of making same

Patent metadata

Field	Value
Publication number	US-10861869-B2
Application number	US-201916242245-A
Country	US
Kind code	B2
Filing date	Jan 8, 2019
Priority date	Jul 16, 2018
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes respective charge storage elements and a respective vertical semiconductor channel contacting an inner sidewall of the respective charge storage elements. The sacrificial material layers are replaced with electrically conductive layers. A polycrystalline aluminum oxide blocking dielectric layer is provided between each charge storage element and a neighboring one of the electrically conductive layers. The polycrystalline aluminum oxide blocking dielectric layer is formed by: depositing an amorphous aluminum oxide layer, converting the amorphous aluminum oxide layer into an in-process polycrystalline aluminum oxide blocking dielectric layer, and by thinning the in-process polycrystalline aluminum oxide blocking dielectric layer.

First claim

What is claimed is:

1. A method of forming a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
forming a memory stack structure through the alternating stack, wherein the memory stack structure comprises a vertical semiconductor channel laterally surrounded by a vertical stack of charge storage elements; and
replacing the sacrificial material layers with material portions comprising electrically conductive layers,

wherein:
a polycrystalline aluminum oxide blocking dielectric layer is provided between each charge storage element and a neighboring one of the electrically conductive layers; and
the polycrystalline aluminum oxide blocking dielectric layer is formed by:
depositing an amorphous aluminum oxide layer;
converting the amorphous aluminum oxide layer into an in-process polycrystalline aluminum oxide blocking dielectric layer by an anneal; and
thinning the in-process polycrystalline aluminum oxide blocking dielectric layer into the polycrystalline aluminum oxide layer by etching back a surface portion of the in-process polycrystalline aluminum oxide blocking dielectric layer using an etch process;
wherein:
the amorphous aluminum oxide layer is deposited directly on physically exposed surfaces of the insulating layers;
the in-process polycrystalline aluminum oxide blocking dielectric layer comprises an edge at which a physically exposed vertical surface of the in-process polycrystalline aluminum oxide blocking dielectric layer directly adjoins a physically exposed horizontal surface of the in-process polycrystalline aluminum oxide blocking dielectric layer; and
the etch process removes the edge and forms a concave surface having a uniform radius of curvature within a region in which a physically exposed vertical surface of the polycrystalline aluminum oxide blocking dielectric layer indirectly adjoins a physically exposed horizontal surface of the polycrystalline aluminum oxide blocking dielectric layer through the concave surface.

2. The method of claim 1 , wherein the etch process comprises an isotropic etch process that reduces a thickness of a vertical portion of the in-process polycrystalline aluminum oxide blocking dielectric layer by a percentage in a range from 15% to 85%.

3. The method of claim 1 , wherein the radius of curvature is the same as an etch distance of the etch process.

4. The method of claim 1 , further comprising:
forming a memory opening through the alternating stack, wherein a sidewall of the memory opening comprises physically exposed surfaces of layers within the alternating stack; and
forming the amorphous aluminum oxide layer on the sidewall of the memory opening.

5. The method of claim 4 , further comprising conformally depositing a charge storage layer on the polycrystalline aluminum oxide layer, wherein the charge storage layer comprises the vertical stack of charge storage elements.

6. The method of claim 5 , further comprising:
forming backside recesses by removing the sacrificial material layers selective to the insulating layers and the polycrystalline aluminum oxide layer; and
depositing an element selected from a backside blocking dielectric layer and one of the electrically conductive layers directly on physically exposed surface portions of the polycrystalline aluminum oxide layer within the backside recesses.

7. The method of claim 1 , further comprising
forming backside recesses by removing the sacrificial material layers selective to the insulating layers and the memory stack structure;
forming the amorphous aluminum oxide layer on physically exposed surfaces of the insulating layers and the memory stack structure in the backside recesses.

8. The method of claim 7 , further comprising depositing the electrically conductive layers directly on the polycrystalline aluminum oxide layer.

9. The method of claim 1 , further comprising:
forming stepped surfaces by patterning the alternating stack, wherein each of the sacrificial material layers other than a bottommost one of the sacrificial material layers laterally extends farther than any overlying one of the sacrificial material layers;
forming a retro-stepped dielectric material portion over the stepped surfaces; and
forming contact via structures directly on a respective one of the electrically conductive layers.

Assignees

• Sandisk Technologies Llc

Inventors

• Nakamura Ryo
• Ueda Yu
• Hinoue Tatsuya
• Inoue Shigehisa
• Mizuno Genta
• Tsutsumi Masanori

Classifications

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H01L27/11565

  Electricity · mapped topic

• H01L29/40117

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic