Semiconductor structure with concave blocking dielectric sidewall and method of making thereof by isotropically etching the blocking dielectric layer

Patent metadata

Field	Value
Publication number	US-9478558-B2
Application number	US-201514600226-A
Country	US
Kind code	B2
Filing date	Jan 20, 2015
Priority date	Jan 20, 2015
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A spacer with a bottom opening is formed over the first blocking dielectric layer by deposition of a conformal material layer and an anisotropic etch. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched by an isotropic etch process that minimizes overetch into the substrate. An optional additional blocking dielectric layer, at least one charge storage element, a tunneling dielectric, and a semiconductor channel can be sequentially formed in the memory opening to provide a three-dimensional memory stack.

First claim

What is claimed is:

1. A method of fabricating a memory device, comprising:
forming a stack including an alternating plurality of material layers and insulator layers over a substrate;
forming a memory opening extending through the stack;
forming a first blocking dielectric layer in the memory opening and over the stack;
forming a continuous material layer over the first blocking dielectric layer;
forming a spacer by anisotropically etching the continuous material layer, wherein a top surface of a horizontal portion of the first blocking dielectric layer is physically exposed within an opening in the spacer;
etching the horizontal portion of the first blocking dielectric layer at a bottom of the memory opening through the opening in the spacer, whereby a top semiconductor surface of the substrate is physically exposed at a bottom of the memory opening;
forming a memory material layer comprising a charge trapping material or patterned conductive material portions over the top semiconductor surface of the substrate and over a sidewall of the spacer within the memory opening after the continuous material layer is patterned into the spacer; and
forming a tunneling dielectric layer and a semiconductor channel over the memory material layer.

2. The method of claim 1 , further comprising forming an additional blocking dielectric layer directly on the substrate prior to forming the memory material layer.

3. The method of claim 2 , wherein the additional blocking dielectric layer is formed by conformal deposition of a dielectric material.

4. The method of claim 3 , wherein the additional blocking dielectric layer is deposited on an inner sidewall of the spacer.

5. The method of claim 4 , wherein the additional blocking dielectric layer is a silicon oxide layer.

6. The method of claim 3 , further comprising removing the spacer selective to the first blocking dielectric layer, wherein the additional blocking dielectric layer is deposited on a sidewall of the first blocking dielectric layer and the top semiconductor surface of the substrate.

7. The method of claim 3 , wherein a bottommost surface of the additional blocking dielectric layer is formed within a horizontal plane including a bottommost surface of the first blocking dielectric layer.

8. The method of claim 3 , further comprising:
forming a disposable dielectric layer by converting the spacer into a first dielectric material portion and converting a surface portion of the substrate into a second dielectric material portion, wherein the disposable dielectric layer comprises the first dielectric material portion and the second dielectric material portion; and
removing the disposable dielectric layer selective to the first blocking dielectric layer and a semiconductor material of the substrate.

9. The method of claim 8 , wherein the additional blocking dielectric layer is deposited on a sidewall of the first blocking dielectric layer and a top surface of a remaining portion of the substrate that remains after converting the surface portion of the substrate.

10. The method of claim 8 , wherein a bottommost surface of the additional blocking dielectric layer is formed below a horizontal plane including a bottommost surface of the first blocking dielectric layer.

11. The method of claim 2 , wherein the additional blocking dielectric layer is formed by simultaneous conversion of the spacer into a first dielectric material portion and a surface portion of the substrate into a second dielectric material portion.

12. The method of claim 11 , wherein the spacer comprises a semiconductor material.

13. The method of claim 12 , wherein the first dielectric material portion comprises a dielectric oxide including a compound of at least one semiconductor element in the semiconductor material and oxygen.

14. The method of claim 11 , wherein the spacer comprises a dielectric nitride.

15. The method of claim 14 , wherein the first dielectric material portion comprises a dielectric oxide or a dielectric oxynitride, and is formed by oxidation of the dielectric nitride.

16. The method of claim 11 , wherein a periphery of the first dielectric material portion is adjoined to a periphery of a bottom portion of the second dielectric material portion.

17. The method of claim 11 , wherein the first dielectric material portion and the second dielectric material portion have different material compositions.

18. The method of claim 11 , wherein:
a bottom surface of the second dielectric material portion is located below a horizontal plane including a bottom surface of the first blocking dielectric layer; and
a top surface of the second dielectric material portion is located above the horizontal plane including the bottom surface of the first blocking dielectric layer.

19. The method of claim 1 , wherein the memory material layer is deposited directly on the spacer and the top semiconductor surface of the substrate.

20. The method of claim 19 , wherein a bottommost surface of the memory material layer is coplanar with a bottom surface of the first blocking dielectric layer.

21. The method of claim 1 , wherein etching of the horizontal portion of the first blocking dielectric layer forms a peripheral undercut cavity by removing a peripheral portion of the first blocking dielectric layer underneath the spacer.

22. The method of claim 21 , further comprising forming an additional blocking dielectric layer directly on the substrate and in the peripheral undercut cavity prior to forming the memory material layer.

23. The method of claim 21 , wherein the memory material layer is deposited in the peripheral undercut cavity.

24. The method of claim 1 , wherein the first blocking dielectric layer comprises a dielectric metal oxide having a dielectric constant greater than 7.9.

25. The method of claim 1 , wherein the first blocking dielectric layer comprises aluminum oxide.

26. The method of claim 1 , wherein the memory material layer comprises a charge trapping material or a floating gate material.

27. The method of claim 1 , further comprising:
removing the material layers from the stack selective to the insulator layers to form a plurality of backside recesses; and
forming a plurality of electrically conductive layers in the plurality of backside recesses.

28. The method of claim 27 , wherein:
the memory device comprises a vertical NAND device; and
at least one of the electrically conductive layers in the stack comprises, or is electrically connected to, a word line of the vertical NAND device.

29. The method of claim 28 , wherein:
the NAND device comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;
the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;
the electrically conductive layers in the stack comprise, or are in electrical contact wi

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Koka Sateesh
• Kanakamedala Senaka
• Makala Raghuveer S
• Sharangpani Rahul
• Zhang Yanli
• Lee Yao-Sheng
• Matamis George

Classifications

• H10P50/283

  by chemical means · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D64/015

  removing at least parts of gate spacers, e.g. disposable spacers · CPC title

• H10D30/683

  programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling · CPC title