Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10854709-B2
Application number	US-201916392097-A
Country	US
Kind code	B2
Filing date	Apr 23, 2019
Priority date	Sep 19, 2018
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

A method of manufacturing a semiconductor device includes forming a first electrode, forming a preliminary dielectric layer on the first electrode, forming a second electrode on the preliminary dielectric layer, and at least partially phase-changing the preliminary dielectric layer to form a dielectric layer. An interfacial energy between the first electrode and the dielectric layer may be less than an interfacial energy between the first electrode and the preliminary dielectric layer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a first electrode;
forming a preliminary dielectric layer on the first electrode;
forming a second electrode on the preliminary dielectric layer; and
at least partially phase-changing the preliminary dielectric layer to form a dielectric layer, an interfacial energy between the first electrode and the dielectric layer being less than an interfacial energy between the first electrode and the preliminary dielectric layer.

2. The method as claimed in claim 1 , wherein:
one or more of the first electrode or the second electrode includes niobium nitride, and
the preliminary dielectric layer and the dielectric layer include hafnium oxide.

3. The method as claimed in claim 2 , wherein:
the preliminary dielectric layer has a monoclinic crystalline phase or an amorphous phase hafnium oxide, and
the dielectric layer has a tetragonal crystalline phase hafnium oxide.

4. The method as claimed in claim 1 , wherein a dielectric constant of the dielectric layer is greater than a dielectric constant of the preliminary dielectric layer.

5. The method as claimed in claim 1 , wherein the preliminary dielectric layer contacts the first electrode and the second electrode.

6. The method as claimed in claim 1 , wherein phase-changing of the preliminary dielectric layer continues toward an inside of the preliminary dielectric layer from one or more of a first interface between the preliminary dielectric layer and the first electrode or a second interface between the preliminary dielectric layer and the second electrode.

7. The method as claimed in claim 1 , wherein phase-changing of the preliminary dielectric layer includes performing an annealing process.

8. The method as claimed in claim 1 , further comprising one or more of:
doping the preliminary dielectric layer with a high-dielectric element; and
doping the dielectric layer with the high-dielectric element.

9. The method as claimed in claim 8 , wherein the high-dielectric element includes one or more of zirconium, aluminum, yttrium, scandium, lanthanum, cerium, dysprosium, or tantalum.

10. The method as claimed in claim 1 , further comprising forming a high-dielectric layer embedded in the preliminary dielectric layer,
wherein the preliminary dielectric layer separates the high-dielectric layer from the first electrode and the second electrode.

11. The method as claimed in claim 10 , wherein the high-dielectric layer includes one or more of zirconium oxide, aluminum oxide, or a lanthanide.

12. A semiconductor device, comprising:
a first electrode;
a second electrode on the first electrode; and
a dielectric layer between the first electrode and the second electrode, the dielectric layer including a first portion adjacent to the first electrode, and a second portion adjacent to the second electrode, the first portion and the second portion having different crystalline phases from each other, wherein an interfacial energy between the first electrode and the first portion of the dielectric layer is less than an interfacial energy between the second electrode and the second portion of the dielectric layer.

13. The semiconductor device as claimed in claim 12 , wherein a dielectric constant of the first portion is greater than a dielectric constant of the second portion.

14. The semiconductor device as claimed in claim 12 , wherein:
the first portion of the dielectric layer includes tetragonal hafnium oxide, and
the second portion of the dielectric layer includes monoclinic or amorphous hafnium oxide.

15. The semiconductor device as claimed in claim 12 , wherein:
the first electrode and the second electrode include different materials from each other, and
the first electrode includes niobium nitride.

16. The semiconductor device as claimed in claim 12 , wherein a thickness of the dielectric layer is about 1 nm to about 10 nm.

17. The semiconductor device as claimed in claim 12 , wherein:
the dielectric layer further includes a high-dielectric layer between the first portion and the second portion,
a dielectric constant of the high-dielectric layer is greater than a dielectric constant of the first portion, and
the dielectric constant of the high-dielectric layer is greater than a dielectric constant of the second portion.

18. The semiconductor device as claimed in claim 12 , further comprising a conductive layer,
wherein the conductive layer is embedded in the first electrode, or is disposed on one surface of the first electrode, the one surface standing opposite to the dielectric layer.

19. The semiconductor device as claimed in claim 18 , wherein the conductive layer includes titanium nitride.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Kyooho
• Kang Sangyeol
• Cho Kyuho
• Kim Eunsun
• Mun Hyosik

Classifications

• H10P14/6544

  to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer · CPC title

• H10W44/601 Primary

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10D1/68

  Capacitors having no potential barriers · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title

• H01L21/02356

  Electricity · mapped topic