Semiconductor devices including diffusion barriers with high electronegativity metals

Patent metadata

Field	Value
Publication number	US-9455259-B2
Application number	US-201514716371-A
Country	US
Kind code	B2
Filing date	May 19, 2015
Priority date	Sep 16, 2014
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A semiconductor device includes a capacitor with reduced oxygen defects at an interface between a dielectric layer and an electrode of the capacitor. The semiconductor device includes a lower metal layer; a dielectric layer on the lower metal layer and containing a first metal; a sacrificial layer on the dielectric layer and containing a second metal; and an upper metal layer on the sacrificial layer. An electronegativity of the second metal in the sacrificial layer is greater than an electronegativity of the first metal in the dielectric layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate comprising a trench and a gate electrode filling a portion of the trench;
a lower metal layer;
a dielectric layer on the lower metal layer opposite the substrate and containing a first metal;
a sacrificial layer on and in direct contact with the dielectric layer and containing oxygen and a second metal, wherein an electronegativity of the second metal in the sacrificial layer is greater than an electronegativity of the first metal in the dielectric layer, and wherein the sacrificial layer is insulated from the lower metal layer by the dielectric layer; and
an upper metal layer on the sacrificial layer.

2. The semiconductor device of claim 1 , wherein the upper metal layer contains a third metal and the electronegativity of the second metal is greater than an electronegativity of the third metal.

3. The semiconductor device of claim 1 , wherein the second metal is molybdenum (Mo) or ruthenium (Ru).

4. The semiconductor device of claim 1 , wherein the sacrificial layer includes a first sacrificial layer containing the second metal, and a second sacrificial layer not including the second metal, wherein the first sacrificial layer is between the second sacrificial layer and the dielectric layer.

5. The semiconductor device of claim 4 , wherein the first sacrificial layer comprises aluminum oxide.

6. The semiconductor device of claim 4 , wherein the first sacrificial layer has a smaller thickness than the second sacrificial layer.

7. The semiconductor device of claim 2 wherein the upper metal layer includes a nitride of the third metal.

8. The semiconductor device of claim 7 , wherein the third metal includes at least one of titanium (Ti), zirconium (Zr), aluminum (Al), hafnium (Hf), tantalum (Ta), niobium (Nb), yttrium (Y), lanthanum (La), vanadium (V), manganese (Mn) and tungsten (W).

9. The semiconductor device of claim 1 , wherein the upper metal layer includes a noble metal.

10. The semiconductor device of claim 9 , wherein the noble metal includes at least one of ruthenium (Ru), platinum (Pt) and iridium (Ir).

11. The semiconductor device of claim 1 , wherein the thickness of the sacrificial layer is in a range of 5 Å to 10 Å.

12. The semiconductor device of claim 1 , wherein the sacrificial layer is a conductive layer.

13. A semiconductor device comprising:
a transistor including first and second impurity regions;
a bit line electrically connected to the first impurity region;
a lower metal layer electrically connected to the second impurity region;
a dielectric layer on the lower metal layer and containing a first metal;
a sacrificial layer on the dielectric layer opposite the lower metal layer and containing a second metal and oxygen, wherein electronegativity of the second metal is greater than that of the first metal and wherein the sacrificial layer is insulated from the lower metal layer by the dialectic layer; and
an upper metal layer formed on and in direct contact with the sacrificial layer, wherein the sacrificial layer is between the dielectric layer and the upper metal layer.

14. The semiconductor device of claim 13 , wherein the lower metal layer has a shape of a cylinder or a pillar.

15. The semiconductor device of claim 13 , wherein the sacrificial layer comprises a first sacrificial layer containing molybdenum (Mo) or ruthenium (Ru), and a second sacrificial layer between the first sacrificial layer and the dielectric layer and containing the aluminum (Al).

16. A semiconductor device comprising:
a substrate;
a lower metal layer;
a dielectric layer on the lower metal layer opposite the substrate and containing a first metal;
a diffusion harrier on and in direct contact with the dielectric layer and containing ruthenium (Ru) or molybdenum (Mo) and oxygen, and wherein the diffusion barrier layer is insulated from the lower metal layer by the dielectric layer; and
an upper metal layer on and in direct contact with the diffusion harrier;
wherein the diffusion barrier is configured to obstruct diffusion of oxygen atoms from the dielectric layer into the upper metal layer and to supply oxygen atoms to the upper metal layer.

17. The semiconductor device of claim 16 , wherein the diffusion barrier is further configured to for an energy barrier that opposes the diffusion of oxygen atoms from the dielectric layer into the upper metal layer.

18. The semiconductor device of claim 16 , wherein the first metal is different from ruthenium (Ru) or molybdenum (Mo) and has a lower electronegativity than ruthenium (Ru) or molybdenum (Mo).

19. The semiconductor device of claim 18 , wherein the diffusion barrier comprises a first sacrificial layer including ruthenium (Ru) or molybdenum (Mo), and a second sacrificial layer between the first sacrificial layer and the dielectric layer and not including ruthenium (Ru) or molybdenum (Mo).

20. The semiconductor device of claim 18 , wherein the upper metal layer comprises metal nitride,
wherein the metal of the metal nitride includes at least one of titanium (Ti), zirconium (Zr), aluminum (Al), hafnium (Hf), tantalum (Ta), niobium (Nb), yttrium (Y), lanthanum (La), vanadium (V), manganese (Mn) and tungsten (W).

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lim Han-Jin
• Kim Youn-Soo
• Park Hyun
• Lee Soon-Gun
• Cho Eun-Ae
• Cho Chin-Moo
• Kim Sung-Jin
• Nam Seok-Woo

Classifications

• H10D1/716

  having vertical extensions · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title

• H01L28/75

  Electricity · mapped topic

• H01L27/10814 Primary

  Electricity · mapped topic