Semiconductor device having capacitor and method of fabricating the semiconductor device

Patent metadata

Field	Value
Publication number	US-9716094-B2
Application number	US-201615229424-A
Country	US
Kind code	B2
Filing date	Aug 5, 2016
Priority date	Oct 2, 2015
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

A semiconductor device having a capacitor includes a substrate which has a transistor, a first insulating pattern which is formed on the substrate and does not overlap a first contact node formed in the substrate, a second insulating pattern which is formed on the substrate, does not overlap a second contact node formed in the substrate, and is separated from the first insulating pattern, a first lower electrode which is formed on part of the substrate and sidewalls of the first insulating pattern, a second lower electrode which is formed on part of the substrate and sidewalls of the second insulating pattern, a dielectric layer pattern which is formed on the first lower electrode and the second lower electrode, and an upper electrode which is formed on the dielectric layer pattern. Related fabrication methods are also discussed.

First claim

What is claimed is:

1. A semiconductor device having a capacitor comprising:
a substrate which has a transistor;
first and second insulating patterns which are on the substrate and separated from each other;
a first lower electrode which is on a first surface of the first insulating pattern and is not formed on a second surface of the first insulating pattern adjacent to the first surface;
a second lower electrode which is not on a third surface of the second insulating pattern which faces the second surface and is on a fourth surface of the second insulating pattern adjacent to the third surface;
a dielectric layer pattern which is on the second and third surfaces to fill a space between the first and second insulating patterns; and
an upper electrode which is on the dielectric layer pattern.

2. The semiconductor device of claim 1 , wherein an upper surface of the upper electrode is higher than upper surfaces of the first and second insulating patterns.

3. The semiconductor device of claim 1 , wherein the dielectric layer pattern between the first and second insulating patterns is lower than upper surfaces of the first and second insulating patterns.

4. The semiconductor device of claim 1 , wherein the first insulating pattern is separated from the second insulating pattern.

5. The semiconductor device of claim 1 , further comprising:
a first insulating layer between the first insulating pattern and the substrate; and
a second insulating layer between the second insulating pattern and the substrate.

6. The semiconductor device of claim 1 , wherein each of the first insulating pattern and the second insulating pattern is shaped like a square pillar in plan view.

7. The semiconductor device of claim 1 , wherein the first lower electrode is not on an upper surface of the first insulating pattern, and the second lower electrode is not on an upper surface of the second insulating pattern.

8. A semiconductor device having a capacitor comprising:
a first insulating pattern which is on a substrate;
a second insulating pattern which is on the substrate and separated from the first insulating pattern in a first direction;
a first lower electrode extending along sidewalls of the first insulating pattern in a height direction of the first insulating pattern and along the substrate in a second direction intersecting the first direction;
a second lower electrode extending along sidewalls of the second insulating pattern in a height direction of the second insulating pattern and along the substrate in the second direction;
a dielectric layer pattern which is on the first and second lower electrodes and between the first and second insulating patterns; and
an upper electrode which is on the dielectric layer pattern.

9. The semiconductor device of claim 8 , wherein the first lower electrode and the second lower electrode are separated from each other in the first direction.

10. The semiconductor device of claim 8 , further comprising:
a first insulating layer which is between the first insulating pattern and the substrate; and
a second insulating layer which is between the second insulating pattern and the substrate.

11. The semiconductor device of claim 10 , wherein the first insulating layer and the second insulating layer are separated from each other in the first direction.

12. A semiconductor device, comprising:
a substrate including transistors thereon, an interlayer insulating layer on the transistors, and contact nodes extending along a surface of the interlayer insulating layer, wherein the contact nodes are electrically coupled to respective source/drain regions of the transistors; and
capacitor structures on the surface of the interlayer insulating layer, the capacitor structures respectively comprising:
an insulating pattern protruding away from the surface of the interlayer insulating layer; and
a lower electrode on opposing sidewalls of the insulating pattern,
wherein the insulating pattern is a distinct structure from that of an adjacent one of the capacitor structures,
wherein the insulating pattern is positioned between respective ones of the contact nodes on the surface of the interlayer insulating layer, and
wherein the opposing sidewalls of the insulating pattern including the lower electrode thereon are coplanar with those of the adjacent one of the capacitor structures.

13. The semiconductor device of claim 12 , wherein the opposing sidewalls of the insulating pattern comprise first opposing sidewalls that are aligned with those of the adjacent one of the capacitor structures along a first direction, and
wherein the insulating pattern further comprises a second sidewall extending between the first opposing sidewalls thereof along a second direction intersecting the first direction, wherein the second sidewall faces that of the adjacent one of the capacitor structures.

14. The semiconductor device of claim 13 , wherein the capacitor structures further comprise a dielectric layer pattern on the lower electrode, and an upper electrode on the dielectric layer pattern, wherein the dielectric layer pattern and the upper electrode continuously extend between the capacitor structures on the substrate.

15. The semiconductor device of claim 14 , wherein the second sidewall of the insulating pattern includes the dielectric layer pattern thereon but is free of the lower electrode.

16. The semiconductor device of claim 15 , wherein the insulating pattern does not overlap with the respective ones of the contact nodes in plan view, and wherein an upper surface of the insulating pattern is free of the lower electrode such that the lower electrode comprises first and second conductive portions that electrically contact the respective ones of the contact nodes and are electrically isolated from each other.

17. The semiconductor device of claim 16 , wherein a portion of the dielectric layer pattern extending between capacitor structures comprises a concave portion that extends towards the substrate beyond the upper surfaces of the insulating pattern, or a convex portion that extends away from the substrate.

18. The semiconductor device of claim 16 , wherein:
the first opposing sidewalls of the insulating pattern extend parallel to each other;
the second sidewall of the insulating pattern extend perpendicular to the first opposing sidewalls; and
the first and second conductive portions continuously extend from the first opposing sidewalls of the insulating pattern, respectively, to and along surfaces of the respective ones of the contact nodes.

19. The semiconductor device of claim 16 , wherein the capacitor structures further respectively comprise:
an insulating layer between the insulating pattern and the surface of the interlayer insulating layer, wherein the insulating layer extends between and does not overlap with the respective ones of the contact nodes in plan view.

20. The semiconductor device of claim 15 , wherein the dielectric layer pattern comprises a material having a dielectric constant of about 1000 or more.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Sang-Yeol
• Im Ki-Vin
• Kim Youn-Soo
• Lim Han-Jin

Classifications

• H01L28/60

  Electricity · mapped topic

• H01L27/10805 Primary

  Electricity · mapped topic

• H10D1/716 Primary

  having vertical extensions · CPC title

• H10D1/692

  Electrodes · CPC title

• H10B12/033

  the capacitor extending over the transistor · CPC title