Three-dimensional memory device containing asymmetric, different size support pillars and method for making the same

Patent metadata

Field	Value
Publication number	US-10854629-B2
Application number	US-201916368007-A
Country	US
Kind code	B2
Filing date	Mar 28, 2019
Priority date	Mar 28, 2019
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

An alternating stack of insulating layers and spacer material layers is formed over a substrate. A staircase region having stepped surfaces is formed by patterning the alternating stack. Memory opening fill structures are formed in a memory array region, and support pillar structures are formed in the staircase region. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. The support pillar structures include first support pillar structures and having a first maximum lateral dimension and second support pillar structures having a second maximum lateral dimension that is less than the first maximum lateral dimension and interlaced with the first support pillar structures. The sacrificial material layers are replaced with electrically conductive layers. The second support pillar structures are positioned interstitially among the first support pillar structures and contact via structures that are formed on the electrically conductive layers to provide additional structural support.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate and comprising a staircase region having stepped surfaces;
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film;
first support pillar structures vertically extending through the staircase region of the alternating stack and having a first maximum lateral dimension; and
second support pillar structures vertically extending through the staircase region of the alternating stack, having a second maximum lateral dimension that is different than the first maximum lateral dimension, and interlaced with the first support pillar structures;
wherein:
each of the memory films of the memory stack structures comprises a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer;
each of the first support pillar structures comprises a respective first dielectric layer stack;
each of the second support pillar structures comprises a respective second dielectric layer stack;
each of the first dielectric layer stacks and the second dielectric layer stacks includes an outer dielectric layer having a same composition and a same thickness as the blocking dielectric layer, a middle dielectric layer having a same composition and a same thickness as the charge storage layer, and an inner dielectric layer having as same composition and a same thickness as the tunneling dielectric layer;
each of the first support pillar structures comprises a first semiconductor channel material portion including a same material as the vertical semiconductor channels and laterally surrounded by a respective first dielectric layer stack;
each of the second support pillar structures comprises a second semiconductor channel material portion including a same material as the vertical semiconductor channels and laterally surrounded by a respective second dielectric layer stack;
each of the memory stack structures contacts a top surface of a respective pedestal channel portion;
each of the first support pillar structures comprises a respective first pedestal semiconductor portion that contacts a bottom surface of a respective one of the first semiconductor channel material portions; and
each of the second support pillar structures comprises a respective second semiconductor channel material portion that underlies, and is vertically spaced from, a respective one of the second semiconductor channel material portions.

2. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate and comprising a staircase region having stepped surfaces;
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film;
first and second backside trenches vertically extending through the alternating stack along a first horizontal direction; and
first and second support pillar structures vertically extending through the staircase region of the alternating stack;
wherein:
the first support pillar structures are arranged in a plurality of rows that are located between the first and second backside trenches;
the plurality of rows comprise first and second boundary rows that extend along the first horizontal direction adjacent to the first and second backside trenches, and at least one inner row that extends along the first horizontal direction between the first and second boundary rows;
the first support pillar structures have the same pitch in the first and second boundary rows and the at least one inner row; and
the second support pillar structures are located between the first support pillar structures in the first and second boundary rows, but are not located in the at least one inner row to provide an asymmetric support pillar configuration.

Assignees

• Sandisk Technologies Llc

Inventors

• Ge Chun
• Yu Jixin
• Yu Fabo
• Li xin yuan
• Zhang Yanli

Classifications

• H01L27/11529

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic