Three-dimensional memory device with angled word lines and method of making thereof

Patent metadata

Field	Value
Publication number	US-9905573-B1
Application number	US-201615251374-A
Country	US
Kind code	B1
Filing date	Aug 30, 2016
Priority date	Aug 30, 2016
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A mesa structure is formed over peripheral devices on a substrate. An alternating stack of insulating layers and spacer material layers is formed over the substrate and the mesa structure. A region of the alternating stack overlying the mesa structure is removed to provide a region in which the layers in the alternating stack extend along a non-horizontal direction that is parallel to the dielectric sidewall of the mesa structure. Memory stack structures and backside contact via structures are formed through another region of the alternating stack that includes horizontally-extending portions of the layers within the alternating stack. The spacer material layers are provided as, or are replaced with, electrically conductive layers. Top surfaces of portions of the electrically conductive layers that extend parallel to the dielectric sidewall of the mesa structure can be contacted by word line contact via structures.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
a mesa structure located over a substrate and having a top surface and at least one dielectric sidewall;
an alternating stack of insulating layers and electrically conductive layers located over the substrate and on the at least one dielectric sidewall of the mesa structure, wherein each of the electrically conductive layers comprises a respective continuously-extending conductive material portion of a homogeneous composition that includes a respective horizontal sub-portion that extends parallel to a top surface of the substrate and a respective non-horizontal sub-portion that extends parallel to the at least one dielectric sidewall of the mesa structure;
memory stack structures extending through a region of the alternating stack that includes the horizontal sub-portions of the electrically conductive layers, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel;
word line contact via structures that contact top surfaces of non-horizontal sub-portions of the electrically conductive layers and embedded in a contact level dielectric layer overlying the alternating stack; and
support pillar structures extending through a first region of the alternating stack that includes the non-horizontal sub-portions of the electrically conductive layers and laterally separating vertical sub-portions of at least one of the electrically conductive layers,
wherein the mesa structure comprises a dielectric mesa structure.

2. The three-dimensional memory device of claim 1 , wherein:
each of the continuously-extending conductive material portions is free of any physical interface therein; and
a top surface of the dielectric mesa structure and a top surface of a first region of the alternating stack that includes the non-horizontal sub-portions of the electrically conductive layers are located within a first horizontal plane that is parallel to the top surface of the substrate.

3. The three-dimensional memory device of claim 2 , wherein a topmost surface of a second region of the alternating stack that includes the horizontal sub-portions of the electrically conductive layers is located within a second horizontal plane that is located below the first horizontal plane.

4. The three-dimensional memory device of claim 3 , further comprising:
a dielectric cap layer overlying the second region of the alternating stack; and
drain contact via structures extending through the dielectric cap layer, overlying the memory stack structures, and having a bottom surface located within the first horizontal plane.

5. The three-dimensional memory device of claim 1 , wherein each electrically conductive layer has a respective uniform thickness throughout a respective horizontal sub-portion and a region of a respective non-horizontal sub-portion.

6. The three-dimensional memory device of claim 1 , further comprising:
a semiconductor device located on the substrate;
a device contact via structure extending through the dielectric mesa structure and contacting the semiconductor device; and
an interconnect line structure contacting a top surface of the device contact via structure and one of the word line contact via structures.

7. The three-dimensional memory device of claim 1 , wherein:
the electrically conductive layers comprise word lines;
each of the support pillar structures comprises a semiconductor fill structure that is not electrically active, a dielectric fill structure, and the memory film;
the support pillar structures have substantially rectangular horizontal cross-sectional areas having a length which is greater than the width by at least two times.

8. The three-dimensional memory device of claim 1 , wherein the at least one dielectric sidewall of the dielectric mesa structure has a taper angle in a range from 30 degrees to 75 degrees with respect to a vertical direction that is perpendicular to the top surface of the substrate.

9. The three-dimensional memory device of claim 1 , wherein:
the at least one dielectric sidewall of the dielectric mesa structure comprises multiple sets of sidewalls;
each set of sidewalls forms a respective lateral indentation having a respective indentation width; and
the electrically conductive layers have respective elongated portions that protrude into respective lateral indentations.

10. The three-dimensional memory device of claim 9 , wherein one of the electrically conductive layers has a top surface including a first region located outside of the lateral indentations and having a first width and a second region extending into one of the lateral indentations and having a second width that is greater than the first width.

11. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a vertical NAND device located over the substrate;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;
the substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

12. A three-dimensional memory device comprising:
a mesa structure located over a substrate and having a top surface and at least one dielectric sidewall;
an alternating stack of insulating layers and electrically conductive layers located over the substrate and on the at least one dielectric sidewall of the mesa structure, wherein each of the electrically conductive layers comprises a respective continuously-extending conductive material portion of a homogeneous composition that includes a respective horizontal sub-portion that extends parallel to a top surface of the substrate and a respective non-horizontal sub-portion that extends parallel to the at least one dielectric sidewall of the mesa structure;
memory stack structures extending through a region of the alternating stack that includes the horizontal sub-portions of the electrically conductive layers, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel; and
word line contact via structures that contact top surfaces of non-horizontal sub-portions of the electrically conductive layers and embedded in a contact level dielectric layer overlying the alternating stack,

wherein:
the mesa structure comprises a dielectric mesa structure;
the at least one dielectric sidewall of the dielectric mesa structure comprises multiple sets of sidewalls;

Assignees

• Sandisk Technologies Llc

Inventors

• Mada Shogo
• Takahashi Akira
• Umeyama Motoki

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L23/535

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H10B43/40

  characterised by the peripheral circuit region · CPC title