Mating backplane for high speed, high density electrical connector

Patent metadata

Field	Value
Publication number	US-10849218-B2
Application number	US-201916578637-A
Country	US
Kind code	B2
Filing date	Sep 23, 2019
Priority date	Nov 21, 2014
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.

First claim

What is claimed is:

1. A printed circuit board comprising:
a plurality of layers including attachment layers and routing layers; and
via patterns formed in one or more of the plurality of layers, each of the via patterns comprising:
first and second signal vias extending through the attachment layers and connecting to respective signal traces on at least one of the routing layers;
ground vias extending through at least the attachment layers; and
non-plated air holes associated with each of the first and second signal vias and extending to a predetermined depth in the plurality of layers, wherein each of the non-plated air holes is located on a first line that passes through one of the first and second signal vias, the first line being perpendicular to a second line that passes through the first and second signal vias.

2. The printed circuit board as defined in claim 1 , wherein the non-plated air holes are located on opposite sides of the first and second signal vias.

3. The printed circuit board as defined in claim 2 , wherein additional non-plated air holes are located on the second line through the first and second signal vias.

4. The printed circuit board as defined in claim 1 , wherein the non-plated air holes have smaller diameters than the first and second signal vias.

5. The printed circuit board as defined in claim 1 , wherein the non-plated air holes extend through the attachment layers of the plurality of layers.

6. The printed circuit board as defined in claim 1 , wherein one or more of the attachment layers includes a ground plane and wherein the ground plane is removed in an area around the first and second signal vias to form an antipad.

7. A printed circuit board comprising:
a plurality of layers including attachment layers and routing layers; and
via patterns formed in one or more of the plurality of layers, each of the via patterns comprising:
first and second signal vias extending through the attachment layers and connecting to respective signal traces on one or more of the routing layers;
ground vias extending through at least the attachment layers; and
shadow vias extending at least through the attachment layers, the shadow vias having smaller diameters than the first and second signal vias, wherein each of the shadow vias is located on a first line that passes through one of the first and second signal vias, the first line being perpendicular to a second line that passes through the first and second signal vias and wherein the shadow vias are located on opposite sides of the signal vias.

8. The printed circuit board as defined in claim 7 , wherein the shadow vias are free of conductive material at least in the attachment layers.

9. The printed circuit board as defined in claim 7 , wherein the shadow vias are plated or filled with a conductive material.

10. The printed circuit board as defined in claim 7 , wherein each of the shadow vias extends to a predetermined depth in the plurality of layers.

11. The printed circuit board as defined in claim 9 , wherein the shadow vias extend through the attachment layers and the routing layers.

12. A printed circuit board comprising:
a plurality of layers including conductive layers separated by dielectric layers;
first and second signal vias forming a differential signal pair, the first and second signal vias extending through one or more of the plurality of layers; and
non-plated air holes associated with each of the first and second signal vias and extending to a predetermined depth in the plurality of layers, wherein each of the non-plated air holes is located on a first line that passes through one of the first and second signal vias, the first line being perpendicular to a second line that passes through the first and second signal vias.

13. The printed circuit board as defined in claim 12 , wherein the non-plated air holes are located on opposite sides of the first and second signal vias.

14. The printed circuit board as defined in claim 12 , wherein the non-plated air holes have smaller diameters than the first and second signal vias.

15. The printed circuit board as defined in claim 12 , further comprising ground vias extending through one or more of the plurality of layers.

16. The printed circuit board as defined in claim 12 , wherein at least one of the conductive layers of the plurality of layers is removed in an area around the first and second signal vias to form an antipad.

17. The printed circuit board as defined in claim 16 , wherein the non-plated air holes are located, at least partially, within the antipads.

18. The printed circuit board as defined in claim 12 , wherein the non-plated air holes are located adjacent to and on opposite sides of each of the first and second signal vias.

Assignees

• Amphenol Corp

Inventors

• Gailus Mark W
• Cartier Jr Marc B
• Sivarajan Vysakh
• Levine David

Classifications

• H05K1/0219 Primary

  Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors · CPC title

• H05K2201/096

  Vertically aligned vias, holes or stacked vias · CPC title

• H05K2201/09318

  Core having one signal plane and one power plane · CPC title

• H05K3/0047

  Drilling of holes · CPC title

• H05K2201/09063

  Holes or slots in insulating substrate not used for electrical connections · CPC title