Three-dimensional integration for qubits on crystalline dielectric

Patent metadata

Field	Value
Publication number	US-10840296-B2
Application number	US-201916673309-A
Country	US
Kind code	B2
Filing date	Nov 4, 2019
Priority date	May 25, 2018
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

Techniques related to a three-dimensional integration for qubits on crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first wafer comprising a first crystalline silicon layer attached to a first patterned superconducting layer, and a second wafer comprising a second crystalline silicon layer attached to a second patterned superconducting layer. The second patterned superconducting layer of the second wafer can be attached to the first patterned superconducting layer of the first wafer. A buried layer can comprise the first patterned superconducting layer and the second patterned superconducting layer. The buried layer can comprise one or more circuits. The superconductor structure can also comprise a transmon qubit that can comprise a Josephson junction and one or more capacitor pads comprising superconducting material. The Josephson junction can comprise a first superconductor contact, a tunnel barrier layer, and a second superconductor contact.

First claim

What is claimed is:

1. A superconductor structure, comprising:
a buried layer between two wafers comprising crystalline silicon, the buried layer comprising:
a first patterned superconducting layer,
a second patterned superconducting layer attached to the first patterned superconducting layer, wherein a first pattern of the first patterned superconducting layer mirrors a second pattern of the second patterned superconducting layer, and the first pattern having a matching mirrored alignment with the second pattern, and
a circuit based on the first pattern and the second pattern; and

a transmon qubit, on a wafer of the two wafers, comprising a Josephson junction.

2. The superconductor structure of claim 1 , wherein the transmon bit further comprises one or more capacitor pads comprising superconducting material.

3. The superconductor structure of claim 2 , wherein the one or more capacitor pads are located on a surface the wafer.

4. The superconductor structure of claim 2 , wherein the one or more capacitor pads are filled vias within a crystalline silicon layer of the wafer.

5. The superconductor structure of claim 1 , wherein the Josephson junction is a planar Josephson junction.

6. The superconductor structure of claim 1 , wherein the Josephson junction is a vertical Josephson junction.

7. The superconductor structure of claim 1 , wherein the transmon qubit is a first transmon qubit, the superconductor structure further comprising a second transmon qubit on the wafer, wherein the Josephson junction of the first transmon qubit is a planar Josephson junction and the second transmon qubit comprises a vertical Josephson junction.

8. The superconductor structure of claim 1 , further comprising:
a surface superconducting layer on at least a portion of the wafer; and
a through silicon via between the surface superconducting layer and the buried layer.

9. The superconductor structure of claim 1 , further comprising:
a surface superconducting layer on at least a portion of the wafer; and
a partial via in a crystalline silicon layer, the partial via comprises a capacitive connection with the buried layer.

10. A method, comprising:
forming a first patterned superconducting layer on a first wafer of a superconductor structure, wherein the first patterned superconducting layer has a first pattern;
forming a second patterned superconducting layer on a second wafer of the superconductor structure, wherein the second patterned superconducting layer has having a second pattern, and the first pattern mirrors the second pattern, and the first wafer and the second wafer comprise crystalline silicon;
creating a buried layer based on attaching the first patterned superconducting layer and the second patterned superconducting layer, wherein the first pattern has a matching mirrored alignment with the second pattern; and
forming a transmon qubit, on the first wafer, comprising a Josephson junction.

11. The method of claim 10 , wherein the forming the transmon qubit comprises forming one or more capacitor pads comprising superconducting material.

12. The method of claim 10 , wherein the comprises forming the one or more capacitor pads comprising forming the one or more capacitor pads on a surface the first wafer of the superconductor structure.

13. The method of claim 10 , wherein the Josephson junction is a planar Josephson junction.

14. The method of claim 10 , wherein the Josephson junction is a vertical Josephson junction.

15. The method of claim 10 , wherein the transmon qubit is a first transmon qubit, further comprising forming a second transmon qubit on the first wafer of the superconductor structure, wherein the Josephson junction of the first transmon qubit is a planar Josephson junction and the second transmon qubit comprises a vertical Josephson junction.

16. A quantum information device, comprising:
a superconductor structure comprising:
a buried layer between two wafers comprising crystalline silicon, the buried layer comprising:
a first patterned superconducting layer,
a second patterned superconducting layer attached to the first patterned superconducting layer, wherein a first pattern of the first patterned superconducting layer mirrors a second pattern of the second patterned superconducting layer, and the first pattern having a matching mirrored alignment with the second pattern, and
a circuit based on the first pattern and the second pattern; and

a transmon qubit, on a wafer of the two wafers, comprising a Josephson junction.

17. The quantum information device of claim 16 , wherein the transmon obit further comprises one or more capacitor pads comprising superconducting material.

18. The quantum information device of claim 16 , wherein the Josephson junction is a planar Josephson junction.

19. The quantum information device of claim 16 , wherein the Josephson junction is a vertical Josephson junction.

20. The quantum information device of claim 16 , wherein the transmon qubit is a first transmon qubit, the superconductor structure further comprising a second transmon qubit on the wafer, wherein the Josephson junction of the first transmon qubit is a planar Josephson junction and the second transmon qubit comprises a vertical Josephson junction.

Assignees

• IBM

Inventors

• Rosenblatt Sami
• Topaloglu Rasit Onur
• Brink Markus

Classifications

• H10P90/1914

  using bonding · CPC title

• H10D48/3835

  Semiconductor qubit devices comprising a plurality of quantum mechanically interacting semiconductor quantum dots, e.g. Loss-DiVincenzo spin qubits · CPC title

• G06N10/40

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title

• H01L39/223

  Electricity · mapped topic

• H01L39/2493

  Electricity · mapped topic