Chip mode isolation and cross-talk reduction through buried metal layers and through-vias

Patent metadata

Field	Value
Publication number	US-9520547-B2
Application number	US-201313838261-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality vias disposed on the first substrate.

First claim

What is claimed is:

1. A method for fabricating a chip surface base, the method comprising:
preparing a first substrate;
forming a plurality of vias in a top surface of the first substrate;
depositing metal fillings into the plurality of vias;
forming a first metal layer on the top surface of the first substrate and in contact with the plurality of vias;
preparing a second substrate;
forming a second metal layer on a top surface of the second substrate;
bonding the first and second substrates at the first and second metal layers so as to form a bonded, buried metal layer;
polishing a bottom surface of the first substrate so as to expose the metal fillings, wherein the resultant structure comprises the first substrate contacting the first metal layer, the second substrate contacting the second metal layer and the first metal layer contacting the second metal layer; and
etching the first and second substrates to fabricate a qubit circuit;
fabricating a qubit circuit, wherein the qubit circuit is on the first substrate and is coupled to a plurality of chip modes, the plurality of chip modes operative to conduct into the metal fillings deposited into the plurality of vias and define a short into the metal layer between the second substrate and the first substrate, wherein the plurality of chip modes have wavelengths longer than distances between vias in the plurality of vias; and
wherein the plurality of vias is arranged in a location on the first substrate such that the plurality of vias isolates the plurality of chip modes between the plurality of vias and the metal layer between the second substrate and the first substrate.

2. The method as claimed in claim 1 , further comprising:
selecting the first and second substrates to reduce dielectric loss tangent at superconducting temperatures.

3. The method as claimed in claim 1 , wherein the plurality of vias is etched into the top surface of the first substrate.

4. The method as claimed in claim 3 , further comprising: selecting locations of vias on the top surface of the first substrate to correspond to mode locations of the fabricated qubit circuit.

5. The method as claimed in claim 1 , wherein the first and second metal layers are a same material as the metal fillings.

6. The method as claimed in claim 5 , wherein the first and second metal layers and the metal fillings are a superconducting material.

Assignees

• IBM

Inventors

• Abraham David W
• Keefe George A
• Lavoie Christian
• Rothwell Mary E

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W20/4484

  Superconducting materials · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title