Embedding semiconductor devices in silicon-on-insulator wafers connected using through silicon vias

Patent metadata

Field	Value
Publication number	US-9412736-B2
Application number	US-201414296812-A
Country	US
Kind code	B2
Filing date	Jun 5, 2014
Priority date	Jun 5, 2014
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

In an approach to fabricating a silicon on insulator wafer, one or more semiconductor device elements are implanted and one or more shallow trench isolations are formed on a top surface of a first semiconductor wafer. A first dielectric material layer is deposited over the top surface of the first semiconductor wafer, filling the shallow trench isolations. A dielectric material layer on a bottom surface of a second semiconductor wafer is bonded to a dielectric material layer on the top of the first semiconductor wafer and one or more semiconductor devices are formed on a top surface of the second semiconductor wafer. Then, one or more through silicon vias are created connecting the one or more semiconductor devices on the top surface of the second semiconductor wafer and the one or more semiconductor device elements on the top surface of the first semiconductor wafer.

First claim

What is claimed is:

1. A method comprising:
providing a first semiconductor wafer having a first top surface and a first bottom surface opposite the first top surface;
creating one or more semiconductor device elements on the first top surface of the first semiconductor wafer so as to form a first semiconductor device on the first top surface of the first semiconductor wafer;
forming a first dielectric material layer on the first top surface of the first semiconductor wafer over the first semiconductor device;
providing a second semiconductor wafer having a second top surface and a second bottom surface opposite the second top surface;
forming a second dielectric material layer immediately adjacent to the second bottom surface of the second semiconductor wafer;
bonding the second dielectric material layer on the second bottom surface of the second semiconductor wafer directly to the first dielectric material layer on the first top surface of the first semiconductor wafer;
after the bonding, forming at least one second semiconductor device on the second top surface of the second semiconductor wafer; and
creating a through silicon via, the through silicon via extending vertically through the second semiconductor wafer, the second dielectric material layer and the first dielectric material layer to the first semiconductor device and electrically connecting the second semiconductor device on the second top surface of the second semiconductor wafer to the first semiconductor device on the first top surface of the first semiconductor wafer.

2. The method of claim 1 , further comprising:
before the forming of the first dielectric material layer, forming one or more shallow isolation trenches and at least one additional semiconductor device element on the first top surface of the first semiconductor wafer.

3. The method of claim 1 , the first semiconductor device formed on the first top surface of the first semiconductor wafer comprising any one of: a high voltage metal oxide transistor, a laterally diffused metal oxide semiconductor device, an active semiconductor device requiring significant semiconductor wafer area, an active semiconductor device requiring high voltage, an array of active semiconductor devices, a passive semiconductor device and a combination of active semiconductor devices and passive semiconductor devices.

4. The method of claim 1 , further comprising, after the bonding, forming an additional first semiconductor device on the first bottom surface of the first semiconductor wafer, the additional first semiconductor device comprising a doped region within the first semiconductor wafer at the first bottom surface and being any of: an active semiconductor device and a passive semiconductor device.

5. The method of claim 4 , further comprising creating an additional through silicon via connecting a second semiconductor device on the second top surface of the second semiconductor wafer to the additional first semiconductor device on the first bottom surface of the first semiconductor wafer.

6. The method of claim 4 , further comprising creating an additional through silicon via connecting the first semiconductor device on the first top surface of the first semiconductor wafer to the additional first semiconductor device on the first bottom surface of the first semiconductor wafer.

7. The method of claim 1 , further comprising thinning the first semiconductor wafer by grinding the first bottom surface.

8. The method of claim 7 , further comprising:
after the thinning, creating additional through silicon vias extending vertically from the first bottom surface of the first semiconductor wafer to and in contact with the first semiconductor device; and
after the creating of the additional through silicon vias, attaching a heat sink to the first bottom surface of the first semiconductor wafer, the heat sink being immediately adjacent to the additional through silicon vias.

9. The method of claim 8 , the additional through silicon vias having a diameter larger than a diameter of the through silicon via connecting the second semiconductor device to the first semiconductor wafer.

10. A method comprising:
providing a first semiconductor wafer having a first top surface and a first bottom surface opposite the first top surface;
creating one or more semiconductor device elements on the first top surface of the first semiconductor wafer so as to form a first semiconductor device on the first top surface of the first semiconductor wafer;
forming a first dielectric material layer on the first top surface of the first semiconductor wafer over the first semiconductor device, the first bottom surface of the first semiconductor wafer being bonded directly to an additional dielectric material layer over an additional semiconductor device on an additional semiconductor wafer prior to formation of the first semiconductor device and the first dielectric material layer;
providing a second semiconductor wafer having a second top surface and a second bottom surface opposite the second top surface;
forming a second dielectric material layer immediately adjacent to the second bottom surface of the second semiconductor wafer;
bonding the second dielectric material layer on the second bottom surface of the second semiconductor wafer directly to the first dielectric material layer on the first top surface of the first semiconductor wafer;
after the bonding, forming second semiconductor devices on the second top surface of the second semiconductor wafer; and
creating a first through silicon via and a second through silicon via, the first through silicon via extending vertically through the second semiconductor wafer, the second dielectric material layer and the first dielectric material layer to the first semiconductor device and electrically connecting a first one of the second semiconductor devices to the first semiconductor device and the second through silicon via extending vertically through the second semiconductor wafer, the second dielectric material layer, the first dielectric material layer, the first semiconductor wafer and the additional dielectric material layer to the additional semiconductor device and electrically connecting a second one of the second semiconductor devices to the additional semiconductor device.

11. The method of claim 10 , the first semiconductor device and the additional semiconductor device comprising passive semiconductor devices.

12. The method of claim 10 , the first semiconductor device and the additional semiconductor device comprising any of at least one active semiconductor device and a combination of at least one active semiconductor device and at least one passive semiconductor device.

13. A structure comprising:
a first semiconductor wafer having a first bottom surface and a first top surface opposite the first bottom surface, the first semiconductor wafer comprising a first semiconductor device on the first top surface of the first semiconductor wafer;
a first dielectric material layer on the first top surface covering the first semiconductor device;
a second semiconductor wafer having a second top surface and a second bottom surface opposite the second top surface, the second semiconductor wafer comprising a second semiconductor device on the second top surface of the second semiconductor wafer;
a second dielectric material layer immediately adjacent to the second bottom surface of the second semiconductor wafer, the second dielectric material layer being bonded to the first dielectric material layer;
a through silicon via that extends vertically through the second semiconductor wafer, the second dielectric material

Assignees

• Globalfoundries Inc

Inventors

• Ding Yan
• Jain Vibhor
• Kessler Thomas
• Ngu Yves T
• Rassel Robert M
• Ventrone Sebastian T

Classifications

• H10W20/218

  in silicon-on-insulator [SOI] wafers · CPC title

• H10W40/228

  the projecting parts being wire-shaped or pin-shaped · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title