Capacitors

Patent metadata

Field	Value
Publication number	US-10170540-B2
Application number	US-201715417932-A
Country	US
Kind code	B2
Filing date	Jan 27, 2017
Priority date	Jun 11, 2015
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between adjacent wiring lines. The method further includes forming an air gap within spacing between the adjacent wiring lines by deposition of a capping material. The method further includes opening the air gap between selected adjacent wiring lines. The method further includes depositing conductive material within the opened air gap.

First claim

What is claimed:

1. A method comprising:
forming separate wiring lines on a substrate, with spacing between adjacent separate wiring lines;
forming air gaps within the spacing by depositing capping material on the separate wiring lines and the spacing between the adjacent separate wiring lines;
forming a dielectric material over the capping material;
forming a trench in the dielectric material and over plural ones of the adjacent separate wiring lines, wherein the forming the trench opens the air gaps by removing a surface of the capping material; and
depositing conductive material within the opened air gaps through the trench.

2. The method of claim 1 , wherein the separate wiring lines comprise plural metal lines formed directly on a single insulator layer, and the capping material is a dielectric material which directly contacts sidewalls of the separate wiring lines.

3. The method of claim 1 , further comprising depositing conductive material in the trench followed by a reflow process.

4. The method of claim 3 , wherein the conductive material is copper.

5. The method of claim 1 , further comprising forming an interconnect trench simultaneously with the trench over the spacing between other ones of the adjacent separate wiring lines that are separate from the plural ones of the adjacent separate wiring lines.

6. The method of claim 5 , wherein the trench is over the spacing between the plural ones of the adjacent separate wiring lines formed by an initial punchthrough etching step, following by an etching of remaining portions and the interconnect trench.

7. The method of claim 5 , wherein a bottom surface of the trench is lower than a top surface of the capping material, and a bottom surface of the interconnect trench is higher than the top surface of the capping material, such that the interconnect trench and the trench have offset depths.

8. The method of claim 1 , wherein the forming of the air gaps includes pinching off the capping material.

9. The method of claim 1 , wherein the depositing conductive material within the trench includes depositing the conductive material within plural ones of the air gaps through the trench.

10. The method of claim 1 , wherein the capping material is a dielectric material.

11. The method of claim 10 , wherein the capping material is a nitride material.

12. The method of claim 1 , wherein the air gaps are pinched off material of the dielectric layer.

13. The method of claim 1 , wherein the trench is formed by a RIE process.

Assignees

• IBM

Inventors

• Basker Veeraraghavan S
• Cheng Kangguo
• Penny Christopher J
• Standaert Theodorus E
• Wang Junli

Classifications

• H10P50/283

  by chemical means · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title