Capacitors

Patent metadata

Field	Value
Publication number	US-9607943-B2
Application number	US-201514736881-A
Country	US
Kind code	B2
Filing date	Jun 11, 2015
Priority date	Jun 11, 2015
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between adjacent wiring lines. The method further includes forming an air gap within spacing between the adjacent wiring lines by deposition of a capping material. The method further includes opening the air gap between selected adjacent wiring lines. The method further includes depositing conductive material within the opened air gap.

First claim

What is claimed:

1. A method, comprising: forming wiring lines on a substrate, with spacing between adjacent wiring lines;
forming an air gap within spacing between the adjacent wiring lines by deposition of a capping material on both the wiring lines and the spacing between the adjacent wiring lines;
opening the air gap between selected adjacent wiring lines,
wherein a number of the selected adjacent wiring lines is less than a total number of the wiring lines;
and depositing conductive material within the opened air gap.

2. The method of claim 1 , wherein the forming of the air gap includes pinching off the capping material deposited within the spacing prior to the spacing being completely filled.

3. The method of claim 1 , wherein the capping material is a dielectric material.

4. The method of claim 3 , wherein the capping material is a nitride material.

5. The method of claim 1 , wherein the forming of the opening of the air gap comprises:
forming dielectric material over the capping material;
patterning the dielectric material to form a trench over the spacing between selected adjacent wiring lines and the selected adjacent wiring lines; and
continuing the patterning of the dielectric material until the opening is formed above air gap.

6. The method of claim 5 , wherein the conductive material is formed in the trench followed by a reflow process.

7. The method of claim 6 , wherein the conductive material is copper.

8. The method of claim 5 , wherein dielectric material remains between predetermined wiring lines after the patterning.

9. The method of claim 5 , further comprising forming an interconnect trench simultaneously with the trench over the spacing between selected adjacent wiring lines.

10. The method of claim 9 , wherein the trench over the spacing between selected adjacent wiring lines is formed by a reverse RIE lag.

11. The method of claim 9 , wherein the trench over the spacing between selected adjacent wiring lines is formed by an initial punchthrough etching step, following by an etching of remaining portions and the interconnect trench.

12. A method comprising:
forming wiring lines on a substrate, with spacing between adjacent wiring lines;
forming an air gap within the spacing by depositing capping material on the wiring lines and within the spacing between the adjacent wiring until the capping material becomes pinched off;
forming a dielectric material over the capping material including over the air gaps;
forming a trench in the dielectric material over the air gaps;
removing a bottom surface of the trench and underlying capping material to open the air gaps; and
depositing conductive material within the trench and within the opened air gaps.

13. The method of claim 12 , wherein the capping material is a dielectric material which coats sidewalls of the wiring lines.

14. The method of claim 12 , wherein the trench is formed by a reverse RIE lag process.

15. The method of claim 12 , wherein the deposition of the conductive material in the trench is followed by a reflow process.

16. The method of claim 15 , wherein the conductive material is copper.

17. The method of claim 12 , further comprising forming an interconnect trench simultaneously with the trench over the spacing between selected adjacent wiring lines.

18. The method of claim 17 , wherein the trench over the spacing between selected adjacent wiring lines is formed by an initial punchthrough etching step, following by an etching of remaining portions and the interconnect trench.

Assignees

• IBM

Inventors

• Basker Veeraraghavan S
• Cheng Kangguo
• Penny Christopher J
• Standaert Theodorus E
• Wang Junli

Classifications

• H10P50/283

  by chemical means · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title