Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices

Patent metadata

Field	Value
Publication number	US-2016232105-A1
Application number	US-201615098637-A
Country	US
Kind code	A1
Filing date	Apr 14, 2016
Priority date	Apr 8, 2004
Publication date	Aug 11, 2016
Grant date	—

Abstract

A secure demand paging system ( 1020 ) includes a processor ( 1030 ) operable for executing instructions, an internal memory ( 1034 ) for a first page in a first virtual machine context, an external memory ( 1024 ) for a second page in a second virtual machine context, and a security circuit ( 1038 ) coupled to the processor ( 1030 ) and to the internal memory ( 1034 ) for maintaining the first page secure in the internal memory ( 1034 ). The processor ( 1030 ) is operable to execute sets of instructions representing: a central controller ( 4210 ), an abort handler ( 4260 ) coupled to supply to the central controller ( 4210 ) at least one signal representing a page fault by an instruction in the processor ( 1030 ), a scavenger ( 4220 ) responsive to the central controller ( 4210 ) and operable to identify the first page as a page to free, a virtual machine context switcher ( 4230 ) responsive to the central controller ( 4210 ) to change from the first virtual machine context to the second virtual machine context; and a swapper manager ( 4240 ) operable to swap in the second page from the external memory ( 1024 ) with decryption and integrity check, to the internal memory ( 1034 ) in place of the first page.

First claim

1 - 26 . (canceled)

27 . A secure demand paging system, comprising:
a secure memory having memory elements with physical addresses; a non-volatile memory; a volatile page swap memory; a decryption module; a hash module; wherein said decryption module and said hash module are arranged between said secure memory and said non-volatile memory to allow for decryption and integrity verification of data stored in said non-volatile memory during a transfer to said secure memory; and further wherein said secure memory and said volatile page swap memory are connected such that said non-volatile memory may be bypassed during a page swap.

28 . The secure demand paging system of claim 27 , further comprising:
a memory management unit responsive to virtual addresses in a virtual address space; a table in said secure memory relating said physical addresses to said virtual addresses.

29 . The secure demand paging system of claim 28 , wherein said table includes entries identifying whether a page slot in said virtual address space is empty.

30 . The secure demand paging system of claim 28 , wherein said table includes entries identifying swap status for a page slot.

31 . The secure demand paging system of claim 28 , wherein said table includes entries identifying whether a page slot is swapped in, swapped out, or swapped in after being swapped out.

32 . The secure demand paging system of claim 27 , wherein said processor is further operable to select code and data pages differently in priority for swap out.

33 . The secure demand paging system of claim 27 , wherein said processor is further operable to select pages differently in priority for modified or unmodified pages for page fault on read and for page fault on write.

Assignees

• Texas Instruments Inc

Inventors

• Goss Steven C
• Conti Gregory Remy Philippe
• Shankar Narendar M
• Akkar Mehdi-Laurent
• Vial Aymeric

Classifications

• H10P74/232

  comprising connection or disconnection of parts of a device in response to a measurement · CPC title

• H10W20/493

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• G06F12/12

  Replacement control · CPC title

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title