Managing cache memory in a parallel processing environment

Patent metadata

Field	Value
Publication number	US-9639487-B1
Application number	US-201615083408-A
Country	US
Kind code	B1
Filing date	Mar 29, 2016
Priority date	Apr 14, 2006
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a plurality of tiles, each tile comprising
a processor; and
switching circuitry including a switch to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles;

a protection system that comprises:
a storage device storing a minimum protection level value for one or more protected resources within the integrated circuit, with the value being the minimum protection level that is needed to complete a desired action using one of the one or more protected resources without causing a fault; and
one or more storage devices storing current protection levels that indicate current protection levels of corresponding portions of a tile, which portions of the tile configured to perform actions using the one or more protected resources, with the protection system configured to:
compare the minimum protection level value associated with the resource with the current protection level value of a portion of the tile taking a desired action, and when the minimum protection level is greater than the current protection level value, the protection system causes a fault to occur and generates an interrupt.

2. The integrated circuit of claim 1 wherein the interrupt is generated before the violating action completes.

3. The integrated circuit of claim 1 wherein the generated interrupt interrupts the processor using an associated interrupt handler.

4. The integrated circuit of claim 3 wherein the associated interrupt handler is executed at the minimum protection level.

5. The integrated circuit of claim 1 wherein comparing occurs before an action associated with a protected resource is completed.

6. The integrated circuit of claim 1 wherein the storage device storing the minimum protection level value is a register, and a process running on the processor sets the minimum protection level value in the register.

7. The integrated circuit of claim 6 wherein a process executing with a current protection level value at or above the minimum value contained in a minimum protection level register is allowed to change the minimum protection level value stored in the register to a lower or a higher minimum protection level value up to the associated current protection level value without causing a fault.

8. The integrated circuit of claim 6 wherein when a process attempts to change a minimum protection level register value that stores a higher value than the associated current protection level value, the protection system generates a protection violation interrupt at the protection level value stored in the minimum protection level register.

9. The integrated circuit of claim 6 wherein if a process attempts to change an minimum protection level register value to a value that is a higher value than the associated current protection level register value, the protection system generates a protection violation interrupt at the protection level of the associated current protection level register value.

10. The integrated circuit of claim 1 wherein the protection system is configured to provide protection at portions of the integrated circuit at which one or more data flows are controlled by generating the interrupt, when a violating data pattern is detected at one or more of the portions of the integrated circuit.

11. The integrated circuit of claim 10 wherein each of the plurality of tiles includes a translation lookaside buffer and the protection system is further configured to:
protect a memory using a physical address lookaside buffer (PALB) that restricts what can be written to a translation lookaside buffer of a tile.

12. The integrated circuit of claim 11 wherein the integrated circuit is configured to execute multiple operating systems on respective sets of the plurality of tiles and the protection system prevents one tile that executes a first one of the multiple operating systems from accessing another tile executing a different one of the multiple operating systems.

13. The integrated circuit of claim 1 wherein the interrupt is asserted before the violating action completes includes delaying committing data associated with the desired action or a subsequent action to the switch by stalling at least a portion of the processor until the interrupt is handled.

14. The integrated circuit of claim 1 wherein the processor comprises at least one pipeline comprising a plurality of stages.

15. The integrated circuit of claim 1 wherein the processor is a Very Long Instruction Word (VLIW) processor configured to process sub-instructions of a VLIW instruction set in respective functional units.

16. A method for processing instructions in an integrated circuit that comprises a plurality of tiles, each tile comprising a processor and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles the method performed by a protection system, the method comprising:
storing in a storage device a minimum protection level value for one or more protected resources within the integrated circuit, with the value being the minimum protection level that is needed to complete a desired action using one or more of the protected resources without causing a fault;
storing in one or more storage devices current protection levels that indicate current protection levels of corresponding portions of a tile, which portions of the tile configured to perform actions using one or more of the protected resources; and
comparing by the protection system the minimum protect level value associated with the resource with the current protection level value of a portion of the tile taking a desired action; and when the minimum value is greater than the current value;
generating by the protection system an interrupt.

17. The method of claim 16 wherein the interrupt is generated before the violating action completes.

18. The method of claim 16 wherein the generated interrupt interrupts the processor using an associated interrupt handler, executed at the minimum protection level.

19. The method of claim 16 wherein the storage device storing the minimum protection level value is a register, and a process running on the processor sets the minimum protection level value in the register, and protection is provided at portions of the integrated circuit at which one or more data flows are controlled.

20. The method of claim 16 wherein each of the plurality of tiles includes a translation lookaside buffer and method further comprises:
protecting a memory using a physical address lookaside buffer (PALB) that restricts what can be written to a translation lookaside buffer of a tile.

21. The method of claim 16 wherein the integrated circuit is configured to execute multiple operating systems on respective sets of the plurality of tiles and the method further comprises:
preventing one tile that executes a first one of the multiple operating systems from accessing another tile executing a different one of the multiple operating systems.

22. A computer program product tangibly stored on a computer readable hardware storage device for processing instructions in an integrated circuit, the integrated circuit including a plurality of tiles, each tile including a processor and a switch including switching circuitry t

Assignees

• Mattina Matthew
• Mellanox Technologies Ltd

Inventors

• Wentzlaff David M
• Mattina Matthew
• Agarwal Anant

Classifications

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F2212/60

  Details of cache memory · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F2212/682

  Multiprocessor TLB consistency · CPC title