Configuration load of a reconfigurable data processor

Patent metadata

Field	Value
Publication number	US-10831507-B2
Application number	US-201816197826-A
Country	US
Kind code	B2
Filing date	Nov 21, 2018
Priority date	Nov 21, 2018
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.

First claim

What is claimed is:

1. A reconfigurable data processor, comprising:
a bus system;
an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to corresponding configurable units;
wherein configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit; and
a configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array, the unit files each comprising a plurality of ordered sub-files, by sending in a sequence of N rounds (R(i) for i=0 to N−1) one unit sub-file of order (i) via the bus system to all of the configurable units including up to (i+1) sub-files in the plurality of configurable units.

2. The processor of claim 1 , wherein the plurality of configurable units includes all the configurable units in the array of configurable units, and the unit file for one or more of the configurable units implements a no-operation configuration.

3. The processor of claim 1 , wherein the configuration data stores in configurable units in the plurality of configurable units comprise serial chains, and the unit configuration load process receives a first sub-file of the unit file particular to the configurable unit from the bus system in one bus cycle, begins pushing the received first sub-file into the serial chain during subsequent bus cycles before a second sub-file of the unit file is received, receives the second sub-file of the unit file particular to the configurable unit from the bus system for a next round of the sequence in a later bus cycle, and begins pushing the received second sub-files into the serial chain during cycles of the sequence after pushing earlier received sub-files into the serial chain.

4. The processor of claim 1 , wherein the array configuration load process includes receiving from a host process, configuration load command identifying a location in memory of the configuration file, and generating one or more memory access requests in response to the command to retrieve the configuration file.

5. The processor of claim 1 , wherein the configuration file includes a plurality of sub-files of unit files for each configurable unit in a plurality of configurable units, the sub-files being arranged in the configuration file in an interleaved fashion that matches the sequence, and wherein the array configuration load process includes routing the sub-files to configurable units based on locations of the sub-files in the configuration file.

6. The processor of claim 1 , wherein a sub-file has a number N of bits of data, and the bus system is configured to transfer N bits of data in one bus cycle.

7. The processor of claim 1 , wherein the array includes more than one type of configurable unit, and the unit files for different types of configurable units include different numbers of sub-files of configuration data.

8. The processor of claim 1 , wherein the unit files for a first type of configurable unit include Z1 sub-files, and the unit files for a second type of configurable unit include Z2 sub-files, where Z1 is less than Z2, and the array configuration load process includes:
retrieving segments of the configuration file including sub-file (i) of the unit files for all of the configurable units of a first type and the second type, for (i) going from 0 to Z1−1, and then retrieving segments of the configuration file including sub-file (i) of the unit files for all of the configurable units of the second type, for (i) going from Z1 to Z2−1.

9. The processor of claim 1 , wherein configurable units in the array of configurable units include respective load complete status logic connected in a daisy chain starting and ending at the array configuration load logic.

10. The processor of claim 1 , wherein configurable units in the plurality of configurable units use routes in the bus system during execution after configuration also used in the configuration load process.

11. The processor of claim 3 , wherein the first sub-file is consumed by the unit configuration load process in the configurable unit before the second sub-file in the plurality of ordered sub-files is received by the configurable unit.

12. The processor of claim 6 , wherein the configuration data stores in configurable units in the plurality of configurable units comprise serial chains, and the unit configuration load process receives a first sub-file of the unit file particular to the configurable unit from the bus system in one bus cycle, pushes the received first sub-file into the serial chain during N subsequent bus cycles, and receives a second sub-file of the unit file particular to the configurable unit from the bus system in a later bus cycle, and pushes the received second sub-files into the serial chain during N subsequent bus cycles after pushing earlier received sub-files into the serial chain.

13. The processor of claim 9 , wherein the array configuration load logic forwards a load complete signal on the daisy chain after the configuration file is distributed, and in each configurable unit in the array, the load complete status logic forwards the load complete signal on the daisy chain when the load complete signal from a previous member of the daisy chain is received and loading of its unit file is completed.

14. The processor of claim 12 , wherein the array includes more than N configurable units.

15. The processor of claim 1 , wherein the bus system includes a top level network including an external data interface and an array interface, and an array level network connected to the array interface and to the configurable units in the array of configurable units.

16. The processor of claim 15 , wherein the array configuration load process includes receiving from a host process, a configuration load command identifying a location in memory of the configuration file, and generating one or more memory access requests via the top level network in response to the command to retrieve the configuration file through the external data interface.

17. The processor of claim 16 , wherein the array configuration load process routes sub-files of the configuration data to configurable units via the array level network using addresses implied by location of the sub-files in the configuration file.

18. A method for operating a reconfigurable data processor comprising a bus system and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units, the method comprising:
distributing a configuration file comprising unit files for a plurality of the configurable units in the array, the unit files each comprising a plurality of ordered sub-files, by sending in a sequence of N rounds (R(i) for i=0 to N−1) one unit sub-file of order (i) via the bus system to all of the configurable units including up to (i+1) sub-files in the plurality of configurable units; and
receiving in the configurable units, the sub-files of a unit file particular to the

Assignees

• Sambanova Systems Inc

Inventors

• Shah Manish K
• Sivaramakrishnan Ram
• Luttrell Mark
• Jackson David Brian
• Prabhakar Raghu
• Jairath Sumti
• Grohoski Gregory Frederick
• Nataraja Pramod

Classifications

• G06F15/7867 Primary

  with reconfigurable architecture · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F9/44505 Primary

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F15/7871 Primary

  Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS · CPC title