Conformal 3D non-planar multi-layer circuitry

Patent metadata

Field	Value
Publication number	US-10827608-B2
Application number	US-201916351250-A
Country	US
Kind code	B2
Filing date	Mar 12, 2019
Priority date	Aug 9, 2012
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

A method for making conformal non-planar multi-layer circuitry is described. The method can include providing a substrate having a non-planar surface and depositing a first conformal dielectric layer on the substrate, the first conformal dielectric layer conforming to the non-planar surface of the substrate and having a non-planar surface. The method can also include applying a first conformal circuitry layer on the first conformal dielectric layer. The method can include depositing a second conformal dielectric layer on the first conformal circuitry layer, the second conformal dielectric layer conforming to a non-planar surface of the first conformal circuitry layer, and applying a second conformal circuitry layer on the second conformal dielectric layer. Successive layers can be sequentially deposited.

First claim

What is claimed is:

1. A method of forming a multi-layer circuit, comprising:
providing a substrate having a first non-planar surface;
forming a conformal circuitry layer over the substrate, the conformal circuitry layer conforming to the first non-planar surface of the substrate, and the conformal circuitry layer having a second non-planar surface;
forming a copper circuitry layer over the conformal circuitry layer, the copper circuitry layer conforming to the second non-planar surface of the conformal circuitry layer, and the copper circuitry layer having a third non-planar surface;
depositing a first conformal dielectric layer over the substrate, the first conformal dielectric layer conforming to the first non-planar surface of the substrate and the first conformal dielectric layer having a fourth non-planar surface; and
drilling at least one micro via into the first conformal dielectric layer, the at least one micro via exposing the conformal circuitry layer,
wherein the copper circuitry layer contacts the conformal circuitry layer through the at least one micro via.

2. The method of claim 1 , further comprising:
depositing a second conformal dielectric layer over the copper circuitry layer, the second conformal dielectric layer conforming to the third non-planar surface of the copper circuitry layer, and the second conformal dielectric layer having a fourth non-planar surface.

3. The method of claim 2 , wherein the depositing the second conformal dielectric layer includes performing a vapor deposition process until the second conformal dielectric layer has a thickness of about 2 mils.

4. The method of claim 1 , wherein the forming of the conformal circuitry layer includes sputtering or electroplating a chromium-copper alloy layer over the substrate.

5. The method of claim 4 , wherein the chromium-copper alloy layer has a thickness of about 1 micron.

6. The method of claim 1 , wherein the forming of the copper circuitry layer includes sputtering or electroplating a chromium-copper alloy layer over the conformal circuitry layer.

7. The method of claim 1 , wherein at least one of the conformal circuitry layer and the copper circuitry layer has a thickness of about 12.7 microns.

Assignees

• Lockheed Corp

Inventors

• Gonya Stephen
• Twigg Kenn
• Patterson Jim

Classifications

• H05K3/4644 Primary

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• H05K1/0298 Primary

  Multilayer circuits · CPC title

• H05K1/053

  the metal substrate being covered by an inorganic insulating layer · CPC title

• H05K1/0284

  Details of three-dimensional rigid printed circuit boards (H05K1/119 takes precedence; shaping of the substrate H05K3/0014) · CPC title

• H05K2203/0315

  Oxidising metal · CPC title