Conformal 3D non-planar multi-layer circuitry

Patent metadata

Field	Value
Publication number	US-9258907-B2
Application number	US-201213570365-A
Country	US
Kind code	B2
Filing date	Aug 9, 2012
Priority date	Aug 9, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A method for making conformal non-planar multi-layer circuitry is described. The method can include providing a substrate having a non-planar surface and depositing a first conformal dielectric layer on the substrate, the first conformal dielectric layer conforming to the non-planar surface of the substrate and having a non-planar surface. The method can also include applying a first conformal circuitry layer on the first conformal dielectric layer. The method can include depositing a second conformal dielectric layer on the first conformal circuitry layer, the second conformal dielectric layer conforming to a non-planar surface of the first conformal circuitry layer, and applying a second conformal circuitry layer on the second conformal dielectric layer. Successive layers can be sequentially deposited. Microvias may provide electrical connections between circuit layers.

First claim

What is claimed is:

1. A method comprising:
providing a substrate having a non-planar surface;
depositing a first conformal dielectric layer on the non-planar surface of the substrate via vapor deposition, the first conformal dielectric layer conforming to the non-planar surface of the substrate and having a non-planar surface;
applying a first conformal circuitry layer on the first conformal dielectric layer, such that the first conformal circuitry layer conforms to the non-planar surface of the first conformal dielectric layer, the first conformal circuitry layer having a non-planar surface and including a first seed layer and a first conductor layer;
depositing a second conformal dielectric layer on the first conformal circuitry layer, the second conformal dielectric layer conforming to the non-planar surface of the first conformal circuitry layer; and
applying a second conformal circuitry layer on the second conformal dielectric layer, the second conformal circuitry layer including a second seed layer and a second conductor layer wherein each of the first and second conductor layers include copper.

2. The method of claim 1 , wherein applying the first conformal circuitry layer includes:
applying the first seed layer on the first conformal dielectric layer;
applying the first conductor layer on the first seed layer;
depositing resist material on the first conductor layer;
patterning the resist material to reveal portions of the first conductor layer and the first seed layer to be etched away;
etching the first conductor layer;
etching the first seed layer;
removing remaining resist material; and
filling and leveling any cavities or voids created during the etching of the first conductor layer and the first seed layer.

3. The method of claim 1 , wherein each of the first and second seed layers include an alloy having chrome and copper.

4. The method of claim 1 , wherein applying the second conformal circuitry layer includes drilling vias in the second conformal dielectric layer.

5. The method of claim 1 , further comprising etching the non-planar surface of the first conformal dielectric layer to roughen the non-planar surface of the first conformal dielectric layer, wherein the etching of the non-planar surface of the first conformal dielectric layer includes oxygen plasma etching.

6. The method of claim 2 , wherein patterning the resist includes laser imaging or ablation.

7. The method of claim 2 , wherein the filling and leveling includes using an epoxy solder mask material to fill and level the voids.

8. A method comprising:
providing a substrate having a non-planar surface;
depositing a first conformal dielectric layer on the substrate, the first conformal dielectric layer conforming to the non-planar surface of the substrate and having a non-planar surface;
applying a first conformal circuitry layer on the first conformal dielectric layer, such that the first conformal circuitry layer conforms to the non-planar surface of the first conformal dielectric layer, the first conformal circuitry layer having a non-planar surface and a copper conductive layer;
depositing a second conformal dielectric layer on the first conformal circuitry layer, the second conformal dielectric layer conforming to the non-planar surface of the first conformal circuitry layer; and
applying a second conformal circuitry layer on the second conformal dielectric layer.

9. The method of claim 8 , wherein depositing the first conformal dielectric layer includes vapor deposition of the first conformal dielectric layer.

10. The method of claim 8 , wherein applying the first conformal circuitry layer includes:
etching the first conformal dielectric layer to roughen a surface of the first conformal dielectric layer;
applying a seed layer on the first conformal dielectric layer;
applying the conductive layer on the seed layer;
depositing resist material on the conductive layer;
etching the resist material to reveal portions of the conductive layer and the seed layer to be etched away;
etching the conductive layer;
etching the seed layer;
removing remaining resist material; and
filling and leveling any voids created during the etching of the conductive layer and the seed layer.

11. The method of claim 10 , wherein the seed layer includes an alloy having chrome and copper.

12. The method of claim 8 , wherein applying the second conformal circuitry layer includes drilling vias in the second conformal dielectric layer.

13. The method of claim 10 , wherein etching the resist includes laser etching.

14. The method of claim 10 , wherein the filling and leveling includes applying an epoxy solder mask material to fill and level the voids.

Assignees

• Gonya Stephen
• Twigg Kenn
• Patterson Jim
• Lockheed Corp

Inventors

• Gonya Stephen
• Twigg Kenn
• Patterson Jim

Classifications

• H05K2201/09018

  Rigid curved substrate · CPC title

• H05K1/09

  Use of materials for the {conductive, e.g. } metallic pattern · CPC title

• H05K1/053

  the metal substrate being covered by an inorganic insulating layer · CPC title

• H05K3/4644 Primary

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• H05K1/0284

  Details of three-dimensional rigid printed circuit boards (H05K1/119 takes precedence; shaping of the substrate H05K3/0014) · CPC title