Fine line 3d non-planar conforming circuit

Patent metadata

Field	Value
Publication number	US-2016338192-A1
Application number	US-201615222333-A
Country	US
Kind code	A1
Filing date	Jul 28, 2016
Priority date	Oct 10, 2014
Publication date	Nov 17, 2016
Grant date	—

Abstract

A method of producing a non-planar conforming circuit on a non-planar surface includes creating a first set of conforming layers. The first set of conforming layers is created by applying an oxide dielectric layer to the surface, applying a conductive material layer to the oxide dielectric layer, applying a resist layer to the conductive material layer, patterning the resist layer according to a desired circuit layout, etching the surface to remove exposed conductive material, and stripping the resist layer. The process may be repeated to form multiple layers of conforming circuits with electrical connections between layers formed by blind microvias. The resulting set of conforming layers can be sealed.

First claim

1 . A method of producing a non-planar conforming circuit, comprising: creating a first set of conforming layers by: applying a conforming oxide dielectric layer to a non-planar surface; applying a conforming conductive material layer on the oxide dielectric layer; applying a conforming resist layer on the conductive material layer; patterning the resist layer according to a desired circuit layout; etching the surface to remove exposed conductive material; and stripping the resist layer to expose conforming circuit lines in the conductive material layer; and sealing the first set of conforming layers.

2 . The method of claim 1 , further comprising: before sealing the first set of conforming layers, creating at least one additional set of conforming layers according to the steps of creating the first set, wherein sealing the first set of conforming layers includes sealing all of the conforming layers.

3 . The method of claim 2 , wherein: in the at least one additional set of conforming layers, after applying a second oxide dielectric layer and before applying a second conductive material layer, etching at least one via hole in the second dielectric layer.

4 . The method of claim 1 , wherein the oxide layer is comprised of aluminum oxide applied by a physical vapor deposition process, and wherein the conductive material is applied by sputtering material onto the oxide layer.

5 . The method of claim 4 , wherein the conductive material includes a titanium layer, a copper layer and a gold layer.

6 . The method of claim 1 , wherein the patterning of the resist layer is done by laser lithography.

7 . The method of claim 1 , wherein a circuit line includes a portion that is no more than 2 mils wide.

8 . The method of claim 1 , wherein the circuit lines include a portion that is no more than 0.05 mil thick.

9 . The method of claim 1 , wherein the oxide layer includes a portion that is no more than 0.3 mil thick.

10 - 20 . (canceled)

Assignees

• Gonya Stephen
• Eiche James Sean
• Patterson James
• Twigg Kenneth R
• Lockheed Corp

Inventors

• Gonya Stephen
• Eiche James Sean
• Patterson James
• Twigg Kenneth R

Classifications

• H05K2201/09872

  Insulating conformal coating · CPC title

• H05K2201/0179

  Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor · CPC title

• H05K3/06

  the conductive material being removed chemically or electrolytically, e.g. by photo-etch process {(semi-additive methods H05K3/108)} · CPC title

• H05K2201/0317

  Thin film conductor layer; Thin film passive component · CPC title

• H05K1/0284 Primary

  Details of three-dimensional rigid printed circuit boards (H05K1/119 takes precedence; shaping of the substrate H05K3/0014) · CPC title