High performance and low power TSPC latch with data agnostic setup and hold time

Patent metadata

Field	Value
Publication number	US-10826469-B2
Application number	US-202016795456-A
Country	US
Kind code	B2
Filing date	Feb 19, 2020
Priority date	Feb 21, 2019
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

A True Single Phase Clock (TSPC) latch design with symmetrical input data paths. A first input data path includes: a first NMOS transistor coupling a gate of a first PMOS transistor to VSS in response to a rising input data signal, and a second PMOS transistor having a gate coupled to a logic low (VSS) input clock signal, whereby the first and second PMOS transistors turn on to couple a data input node to VDD. A second input data path includes: a third PMOS transistor having a gate coupled to a falling input data signal (VSS), a fourth PMOS transistor having a gate coupled to a logic low (VSS) input clock signal, whereby the third and fourth PMOS transistors turn on to couple a gate of a second NMOS transistor to VDD, whereby the second NMOS transistor turns on to couple the data input node to VSS.

First claim

We claim:

1. An electronic structure for implementing a True Single Phase Clock (TSPC) latch design, the electronic structure comprising:
a data input circuit that includes symmetrical input data paths, including a first input data path for a rising input data signal and a second input data path for a falling input data signal, wherein the first input data path includes:
a first NMOS transistor that couples a first node to receive a first supply voltage in response to the rising input data signal, and
a first PMOS transistor and a second PMOS transistor coupled in series between a second voltage supply terminal and a data input node, wherein the first PMOS transistor is turned on in response to the first supply voltage on the first node and the second PMOS transistor is turned on in response to an input clock signal, thereby applying a second supply voltage from the second voltage supply terminal to the data input node,

and wherein the second data path includes:
a third PMOS transistor and a fourth PMOS transistor coupled in series between the second voltage supply terminal and the first node, wherein the third PMOS transistor is turned on in response to the falling input data signal, and the fourth PMOS transistor is turned on in response to the input clock signal, thereby applying the second supply voltage to the first node, and
a second NMOS transistor that couples the first supply voltage to the data input node in response to the second supply voltage on the first node,

wherein the input data circuit further includes a third NMOS transistor coupled between the first node and the first voltage supply terminal, wherein the third NMOS transistor has a gate coupled to receive the input clock signal.

2. The electronic circuit of claim 1 , further comprising a data latch circuit including a feedback inverter that is enabled and disabled in response to the input clock signal and a voltage on the first node.

3. The electronic circuit of claim 2 , wherein the data latch circuit further comprises a feed-forward inverter coupled to the feedback inverter.

4. The electronic circuit of claim 3 , further comprising an output inverter coupled to the data latch circuit, wherein the input data circuit, data latch circuit and output inverter form a TSPC latch.

5. The electronic circuit of claim 4 , wherein the feedback inverter includes a fourth NMOS transistor having a gate coupled to receive the input clock signal, wherein the second PMOS transistor, the fourth PMOS transistor, the third NMOS transistor and the fourth NMOS transistor are the only transistors of the TSPC latch having gates coupled to receive the input clock signal.

6. The electronic circuit of claim 2 , wherein the feedback inverter comprises:
a fifth PMOS transistor having a gate coupled to the first node; and
a fourth NMOS transistor having a gate that receives the input clock signal.

7. The electronic circuit of claim 6 , wherein the feedback inverter further comprises:
a sixth PMOS transistor, wherein the fifth and sixth PMOS transistors are coupled in series between the second voltage supply terminal and the data input node; and
a fifth NMOS transistor, wherein the fourth and fifth NMOS transistors are coupled in series between the data input node and the first voltage supply terminal, wherein a gate of the sixth PMOS transistor and a gate of the fifth NMOS transistor are commonly coupled to form an input terminal of the feedback inverter.

8. The electronic circuit of claim 7 , wherein the data latch circuit further comprises a feed-forward inverter having an input terminal coupled to the data input node and an output terminal coupled to the input terminal of the feedback inverter.

9. An electronic structure having a data input circuit comprising:
a first input data path comprising a first PMOS transistor and a second PMOS transistor coupled in series between a first voltage supply terminal and a first node, and a first NMOS transistor coupled between a second node and a second voltage supply terminal, wherein the first NMOS transistor has a gate coupled to the first node, the first PMOS transistor has a gate that receives an input data signal, and the second PMOS transistor has a gate that receives an input clock signal;
a second input data path comprising a third PMOS transistor and a fourth PMOS transistor coupled in series between the first voltage supply terminal and the second node, and a second NMOS transistor coupled between the first node and the second voltage supply terminal, wherein the first NMOS transistor has a gate that receives the input data signal, the third PMOS transistor has a gate coupled to the first node and the fourth PMOS transistor has a gate that receives the input clock signal; and
a third NMOS transistor coupled between the first node and the second voltage supply terminal, wherein the third NMOS transistor has a gate coupled to receive the input clock signal.

10. The electronic structure of claim 9 , further comprising a data latch circuit coupled to the second node, wherein the data latch circuit is enabled in response to the input clock signal and a voltage on the first node.

11. The electronic structure of claim 10 , wherein the data latch circuit includes a feedback inverter comprising:
a fifth PMOS transistor, a sixth PMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor coupled in series between the first voltage supply terminal and the second voltage supply terminal, wherein the fifth PMOS transistor has a gate coupled to the first node, and the fifth NMOS transistor has a gate that receives the input clock signal.

12. The electronic structure of claim 11 , wherein the data latch circuit includes a feed-forward inverter coupled to the feedback inverter.

13. The electronic structure of claim 12 , further comprising an output inverter coupled to the data latch circuit.

Assignees

• Synopsys Inc

Inventors

• Srivastava Manish
• Jadhav Pradip Subhana

Classifications

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K3/356165 Primary

  using additional transistors in the feedback circuit · CPC title