Voltage level shifters employing preconditioning circuits, and related systems and methods

Patent metadata

Field	Value
Publication number	US-2016359487-A1
Application number	US-201514731747-A
Country	US
Kind code	A1
Filing date	Jun 5, 2015
Priority date	Jun 5, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

Voltage level shifters employing preconditioning circuits are disclosed. Related systems and methods are also disclosed. In one aspect, voltage level shifter is configured to generate a voltage level shifted non-complement output signal and complement output signal corresponding to non-complement input signal and complement input signal, respectively. First pull-up circuit is configured to generate complement output signal in response to non-complement input signal transitioning to logic low voltage. First pull-down circuit is configured to generate non-complement output signal in response to complement input signal transitioning to logic high voltage. First preconditioning circuit is configured to receive non-complement and complement output signals and generate and provide shifted voltage signal to complement output in response to non-complement output signal transitioning to logic low voltage. This allows the complement output signal to transition to the shifted voltage more quickly.

First claim

1 . A voltage level shifter, comprising:
a first pull-up circuit, comprising:
a first input configured to receive a non-complement input signal; and
a second input configured to receive a non-complement output signal;
the first pull-up circuit configured to generate a complement output signal on a first pull-up output coupled to a complement output;
a first pull-down circuit, comprising:
a first input configured to receive a complement input signal;
the first pull-down circuit configured to generate the non-complement output signal comprising a ground voltage signal on a first pull-down output coupled to a non-complement output;
a first preconditioning circuit, comprising:
a first input configured to receive the non-complement output signal; and
a second input configured to receive the complement output signal;
the first preconditioning circuit configured to generate a shifted voltage signal of the complement input signal on a first preconditioning output directly coupled to the complement output in response to the non-complement output signal transitioning to a logic low voltage; and
a fourth preconditioning circuit, comprising:
a first input configured to receive the complement output signal; and
a second input configured to receive the non-complement output signal;
the fourth preconditioning circuit configured to generate the ground voltage signal on a fourth preconditioning output directly coupled to the non-complement output in response to the complement output signal transitioning to a logic high voltage.

2 . The voltage level shifter of claim 1 , wherein the second input of the first preconditioning circuit is coupled to a delay output of a delay circuit, wherein an input of the delay circuit is coupled to the complement output.

3 . The voltage level shifter of claim 1 , further comprising:
a second pull-up circuit, comprising:
a first input configured to receive the complement input signal; and
a second input configured to receive the complement output signal;
the second pull-up circuit configured to generate the non-complement output signal on a second pull-up output coupled to the non-complement output; and
a second pull-down circuit, comprising:
a first input configured to receive the non-complement input signal;
the second pull-down circuit configured to generate the complement output signal comprising the ground voltage signal on a second pull-down output coupled to the complement output.

4 . The voltage level shifter of claim 3 , wherein the first pull-up circuit further comprises:
a first p-type metal-oxide semiconductor (PMOS) transistor, comprising:
a gate configured to receive the non-complement input signal;
a drain coupled to the first pull-up output; and
a source; and
a second PMOS transistor, comprising:
a gate coupled to the non-complement output;
a source coupled to a voltage supply; and
a drain coupled to the source of the first PMOS transistor.

5 . The voltage level shifter of claim 4 , wherein the first pull-down circuit further comprises an n-type metal-oxide semiconductor (NMOS) transistor, comprising:
a gate configured to receive the complement input signal; a drain coupled to the first pull-down output; and a source coupled to a ground voltage source.

6 . The voltage level shifter of claim 5 , wherein the first preconditioning circuit further comprises:
a first PMOS transistor, comprising:
a source coupled to the voltage supply;
a gate coupled to the non-complement output; and
a drain; and
a second PMOS transistor, comprising:
a gate configured to receive the complement output signal;
a source coupled to the drain of the first PMOS transistor of the first preconditioning circuit; and
a drain coupled to the first preconditioning output.

7 . The voltage level shifter of claim 6 , wherein the second pull-up circuit further comprises:
a first PMOS transistor, comprising:
a gate configured to receive the complement input signal;
a drain coupled to the second pull-up output; and
a source; and
a second PMOS transistor, comprising:
a gate coupled to the complement output;
a source coupled to the voltage supply; and
a drain coupled to the source of the first PMOS transistor of the second pull-up circuit.

8 . The voltage level shifter of claim 7 , wherein the second pull-down circuit further comprises an NMOS transistor, comprising:
a gate configured to receive the non-complement input signal; a drain coupled to the second pull-down output; and a source coupled to the ground voltage source.

9 . The voltage level shifter of claim 8 , wherein the first PMOS transistor and the second PMOS transistor of the second pull-up circuit are each configured to have a longer gate length than a gate length of the NMOS transistor of the first pull-down circuit.

10 . The voltage level shifter of claim 8 , wherein the first PMOS transistor and the second PMOS transistor of the second pull-up circuit are each configured to have a shorter gate width than a gate width of the NMOS transistor of the first pull-down circuit.

11 . The voltage level shifter of claim 8 , wherein the first PMOS transistor and the second PMOS transistor of the second pull-up circuit are each configured to have a higher threshold voltage than a threshold voltage of the NMOS transistor of the first pull-down circuit.

12 . The voltage level shifter of claim 8 , wherein the first PMOS transistor and the second PMOS transistor of the first pull-up circuit are each configured to have a longer gate length than a gate length of the NMOS transistor of the second pull-down circuit.

13 . The voltage level shifter of claim 8 , wherein the first PMOS transistor and the second PMOS transistor of the first pull-up circuit are each configured to have a shorter gate width than a gate width of the NMOS transistor of the second pull-down circuit.

14 . The voltage level shifter of claim 8 , wherein the first PMOS transistor and the second PMOS transistor of the first pull-up circuit are each configured to have a higher threshold voltage than a threshold voltage of the NMOS transistor of the second pull-down circuit.

15 . The voltage level shifter of claim 8 , wherein the first PMOS transistor and the second PMOS transistor of the first preconditioning circuit are each configured to have a shorter gate length than a gate length of the first PMOS transistor and the second PMOS transistor of the first pull-up circuit.

16 . The voltage level shifter of claim 8 , wherein the first PMOS transistor and the second PMOS transistor of the first preconditioning circuit are each configured to have a longer gate width than a gate width of the first PMOS transistor and the second PMOS transistor of the first pull-up circuit.

17 . The voltage level shifter of claim 8 , wherein the first PMOS transistor and the second PMOS transistor of the first preconditioning circuit are each configured to have a lower threshold voltage than a threshold voltage of the first PMOS transistor and the second PMOS transistor of the first pull-up circuit.

18 . The voltage level shifter of claim 3 , further comprising:
a second preconditioning circuit, comprising:
a first input configured to receive the non-complement output signal originating from the non-complement output; and
a second input configured to receive the complement output;
the second preconditioning circuit configured to generate a shifted voltage signal of the non-complement input signal on a second preconditioning output directly coupled to the non-co

Assignees

• Qualcomm Inc

Inventors

• Nadkarni Rahul Krishnakumar
• Liles Stephen Edward
• Garg Manish

Classifications

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title

• H03K3/356165

  using additional transistors in the feedback circuit · CPC title

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title