Conditional pulse generator circuit for low power pulse triggered flip flop

Patent metadata

Field	Value
Publication number	US-9401715-B1
Application number	US-201514718204-A
Country	US
Kind code	B1
Filing date	May 21, 2015
Priority date	May 21, 2015
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

An electronic device includes a pulsed latch circuit configured to latch a data input signal to an output based upon receipt of a pulse signal. A pulse generation circuit is configured to compare the data input signal and an output signal at the output of the pulsed latch circuit, and to generate the pulse signal based upon a mismatch therebetween in response to a clock signal.

First claim

The invention claimed is:

1. An electronic device, comprising:
a pulsed latch circuit configured to latch a data input signal to an output based upon receipt of a pulse signal; and
a pulse generation circuit configured to compare the data input signal and an output signal at the output of the pulsed latch circuit, and to generate the pulse signal based upon a mismatch therebetween in response to a clock signal.

2. The electronic device of claim 1 , wherein the pulse generation circuit comprises:
a comparison circuit configured to receive the data input signal and the output signal and to generate a comparison signal based thereupon, the comparison signal having a first logic level when the data input signal and the output signal are mismatched and having a second logic level when the data input signal and the output signal match; and
a comparison output circuit configured to generate a comparison output based upon the comparison signal in response to the clock signal, the comparison output having the first logic level when the comparison signal has the first logic level and having the second logic level when the comparison signal has the second logic level.

3. The electronic device of claim 2 , wherein the comparison circuit comprises:
a first logic circuit having inputs coupled to the output signal and a complement of the data input signal;
a second logic circuit having inputs coupled to a complement of the output signal and the data input signal; and
a comparison node coupled to outputs of the first and second logic circuits.

4. The electronic device of claim 3 , wherein the first logic circuit comprises:
a first PMOS transistor having a source terminal coupled to a supply voltage, a drain terminal, and a gate terminal coupled to the output signal;
a second PMOS transistor having a source terminal coupled to the drain terminal of the first PMOS transistor, a drain terminal coupled to the comparison node, and a gate terminal coupled to the complement of the data input signal.

5. The electronic device of claim 3 , wherein the second logic circuit comprises:
a third PMOS transistor having a source terminal coupled to the supply voltage, a drain terminal, and a gate terminal coupled to the complement of the output signal,
a fourth PMOS transistor having a source terminal coupled to the drain terminal of the third PMOS transistor, a drain terminal coupled to the comparison node, and a gate terminal coupled to the data input signal.

6. The electronic device of claim 2 , wherein the comparison output circuit comprises a fifth PMOS transistor having a source terminal coupled to receive the comparison signal, a drain terminal coupled to a node, and a gate terminal coupled to the clock signal.

7. The electronic device of claim 2 , wherein the pulse generation circuit further comprises:
a first switch circuit configured to receive the comparison output and the clock signal and to generate a first switch output based thereupon, the first switch output having the second logic level based upon the comparison output having the first logic level.

8. The electronic device of claim 7 , wherein the first switch circuit comprises:
a first NMOS transistor having a drain terminal coupled to a first switch output, a source terminal, and a gate terminal coupled to the clock signal; and
a second NMOS transistor having a drain terminal coupled to the source terminal of the first NMOS transistor, a source terminal coupled to ground, and a gate terminal coupled to receive the comparison output.

9. The electronic device of claim 2 , wherein the pulse generation circuit further comprises:
an output circuit configured to receive the first switch output and to generate the pulse signal based thereupon and in response to the clock signal, the pulse signal having the first logic level based upon the first switch output having the second logic level.

10. The electronic device of claim 9 , wherein the output circuit comprises:
a sixth PMOS transistor having a source terminal coupled to a source voltage, a drain terminal coupled to a pulse signal node, and a gate terminal coupled to receive the first switch output; and
a twelfth NMOS transistor having a drain terminal coupled to the pulse signal node, a source terminal coupled to ground, and a gate terminal coupled to receive the first switch output.

11. The electronic device of claim 9 , wherein the pulse generation circuit further comprises a pulse stop circuit configured to cause a transition of the pulse signal based upon the data input signal and the output signal matching, in response to the pulse signal having the first logic level, by discharging the comparison output.

12. The electronic device of claim 11 , wherein the pulse stop circuit comprises:
a second switch circuit having inputs coupled to the clock signal and the first switch output and configured to discharge the comparison output based upon the first switch output having the second logic level, in response to the clock signal;
a third switch circuit having inputs coupled to the data input signal and the output signal and configured to discharge the comparison output based upon the data input signal and the output signal having the second logic level;
a fourth switch circuit having inputs coupled to the complement of the data input signal and the complement of the output signal and configured to discharge the comparison output based upon the complement of the data input signal and the complement of the output signal having the first logic level; and
a pulse stop transistor configured to activate the third and fourth switch circuits based upon the pulse signal having the first logic level.

13. The electronic device of claim 12 , wherein:
the second switch circuit comprises:
a third NMOS transistor having a drain terminal coupled to the node, a source terminal, and a gate terminal coupled to the clock signal,
a fourth NMOS transistor having a drain terminal coupled to the source terminal of the third NMOS transistor, a source terminal coupled to ground, and a gate terminal coupled to the first switch output;

the pulse stop transistor comprises a fifth NMOS transistor having a drain terminal coupled to the node, a source terminal, and a gate terminal coupled to receive the pulse signal;
the third switch circuit comprises:
a sixth NMOS transistor having a drain terminal coupled to the source terminal of the fifth NMOS transistor, a source terminal, and a gate terminal coupled to the data input signal,
a seventh NMOS transistor having a drain terminal coupled to the source terminal of the sixth NMOS transistor, a source terminal coupled to ground, and a gate terminal coupled to the output signal;

the fourth switch circuit comprises:
an eighth NMOS transistor having a drain terminal coupled to the source terminal of the fifth NMOS transistor, a source terminal, and a gate terminal coupled to the complement of the data input signal,
a ninth NMOS transistor having a drain terminal coupled to the source terminal of the eighth NMOS transistor, a source terminal coupled to ground, and a gate terminal coupled to the complement of the output signal.

14. The electronic device of claim 1 , further comprising an output driver coupled to the output of the pulsed latch circuit.

15. An electronic device, comprising:
a comparison circuit configured to receive a data input signal and a latch output signal and to generate a comparison signal based thereupon, the comparison signal having a first signal level when the data input signal and the latch output signal are mismatched and having a second signal level w

Assignees

• St Microelectronics Int Nv

Inventors

• Tripathi Alok Kumar
• Mathuria Priyankar

Classifications

• H03K19/0013 Primary

  in field effect transistor circuits · CPC title

• H03K3/356165

  using additional transistors in the feedback circuit · CPC title

• H03K3/356173

  with synchronous operation · CPC title

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title