Semiconductor device

Patent metadata

Field	Value
Publication number	US-9496870-B2
Application number	US-201514697916-A
Country	US
Kind code	B2
Filing date	Apr 28, 2015
Priority date	Jan 26, 2015
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A semiconductor device is disclosed, which relates to a technology for reducing current consumption of a semiconductor chip configured to operate a transmitter (Tx) at a high speed. The semiconductor device includes a data driving unit configured to output a pull-up drive signal and a pull-down drive signal by level-shifting an input signal according to a clock signal; and a data output unit configured to adjust slew rates of the pull-up drive signal and the pull-down drive signal according to a code signal, and output impedance-adjusted signals to an output terminal.

First claim

What is claimed is:

1. A semiconductor device comprising:
a data driving unit configured to output a pull-up drive signal and a pull-down drive signal by level-shifting an input signal according to a clock signal; and
a data output unit configured to adjust slew rates of the pull-up drive signal and the pull-down drive signal according to a code signal and output impedance-adjusted signals to an output terminal,
wherein the data driving unit includes:
an input unit configured to drive and latch a control signal according to the clock signal and a pulse control signal;
a level shifter configured to level-shift the input signal according to the clock signal when the control signal is activated, and output the output signals according to the level-shifting result;
a pulse generator configured to output the pulse control signal by combining the output signals; and
a drive signal generator configured to pull up or down the pull-up drive signal and the pull-down drive signal according to the output signal.

2. The semiconductor device according to claim 1 , wherein the number of data driving units is plural so that the plural data driving units output the pull-up drive signal through a single pull-up terminal and output the pull-down drive signal through a single pull-down terminal.

3. The semiconductor device according to claim 1 , wherein the input unit includes:
a pull-up drive element electrically coupled between a peri-voltage input terminal and an output terminal of the control signal, configured to be controlled by the clock signal;
a pull-down drive element electrically coupled between an output terminal of the control signal and a ground voltage terminal, configured to be controlled by the pulse control signal; and
a latch unit configured to latch the control signal.

4. The semiconductor device according to claim 1 , wherein the level shifter is configured to level-shift the input signal from a peri-voltage level to a power-supply voltage level when the control signal is activated.

5. The semiconductor device according to claim 1 , wherein the level shifter is configured to precharge an output node by the pulse control signal.

6. The semiconductor device according to claim 1 , wherein the level shifter includes:
a pull-up unit controlled by a signal of an output node, configured to pull the output node up to a power-supply voltage;
a pull-down unit controlled by the input signal, configured to pull the output node down;
an activation unit configured to provide a ground voltage to the pull-down unit upon receiving the clock signal and the pulse control signal; and
an output unit configured to output the output signal by inverting the signal of the output node.

7. The semiconductor device according to claim 6 , wherein the level shifter further includes:
a precharge unit controlled by the pulse control signal to precharge the output node.

8. The semiconductor device according to claim 7 , wherein an output terminal of the precharge unit is electrically coupled to a gate terminal of the pull-up unit.

9. The semiconductor device according to claim 1 , wherein the data output unit includes:
a drive signal input unit configured to delay the pull-up drive signal and the pull-down drive signal;
an adjusting unit configured to control a slew rate of a signal received from the drive signal input unit according to the code signal;
an output driving unit configured to perform pre-driving of an output signal of the adjusting unit;
a pull-up main driving unit configured to pull the output terminal up according to an output signal of the output driving unit; and
a pull-down main driving unit configured to pull the output terminal down according to an output signal of the output driving unit.

10. The semiconductor device according to claim 9 , wherein the adjusting unit includes:
a first adjusting unit electrically coupled to an output terminal of a first drive signal input unit, configured to adjust a slew rate of the pull-up drive signal; and
a second adjusting unit electrically coupled to an output terminal of a second drive signal input unit, configured to adjust a slew rate of the pull-down drive signal.

11. The semiconductor device according to claim 10 , wherein the first adjusting unit includes:
a first resistor electrically coupled to an output terminal of the first drive signal input unit;
a first MOS capacitor electrically coupled to the first resistor;
a first NAND gate configured to perform a logic NAND operation between an output signal of the first resistor and a first code signal;
a second NAND gate configured to perform a logic NAND operation between an output signal of the first drive signal input unit and a second code signal;
a third NAND gate configured to perform a logic NAND operation between an output signal of the first drive signal input unit and a third code signal;
a fourth NAND gate configured to perform a logic NAND operation between an output signal of the first resistor and a fourth code signal;
a second resistor electrically coupled to an output terminal of the first NAND gate; and
a second MOS capacitor electrically coupled to the second resistor.

12. The semiconductor device according to claim 11 , wherein the second adjusting unit includes:
a third resistor electrically coupled to an output terminal of the second drive signal input unit;
a third MOS capacitor electrically coupled to the third resistor;
a fifth NAND gate configured to perform a logic NAND operation between an output signal of the third resistor and a first code signal;
a sixth NAND gate configured to perform a logic NAND operation between an output signal of the second drive signal input unit and a second code signal;
a seventh NAND gate configured to perform a logic NAND operation between an output signal of the second drive signal input unit and a third code signal;
an eighth NAND gate configured to perform a logic NAND operation between an output signal of the second resistor and a fourth code signal;
a fourth resistor electrically coupled to an output terminal of the fifth NAND gate; and
a fourth MOS capacitor electrically coupled to the fourth resistor.

13. The semiconductor device according to claim 9 , wherein the output driving unit includes:
a plurality of pre-drivers configured to perform pre-driving of a pull-up terminal and a pull-down terminal according to the output signal of the adjusting unit.

14. The semiconductor device according to claim 1 , wherein the code signal is generated by Off Chip Driver (OCD) calibration control.

15. A semiconductor device comprising:
a data driving unit configured to output a pull-up drive signal and a pull-down drive signal by driving data; and
a data output unit configured to perform a termination of a data output line according to the pull-up drive signal and the pull-down drive signal and output a termination result to an output terminal,
wherein the data driving unit includes:
an input unit configured to drive and latch a control signal according to a clock signal and a pulse control signal;
a level shifter configured to level-shift the input signal according to the clock signal when the control signal is activated, and output the output signals according to the level-shifting result;
a pulse generator configured to output the pulse control signal by combining the output signals; and
a drive signal generator configured to pull up or down the pull-up drive signal and the pull-down drive signal according to the output signal.

16. The semiconductor device according to claim 15 , further comp

Assignees

• Sk Hynix Inc

Inventors

• Oh Ic Su
• Choi Chang Kyu
• Kwon Dae Han

Classifications

• H03K3/356104

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title

• H03K3/356165

  using additional transistors in the feedback circuit · CPC title

• H03K19/0013 Primary

  in field effect transistor circuits · CPC title

• H03K19/018571

  of complementary type, e.g. CMOS · CPC title

• H03K19/018585

  programmable · CPC title