High density chip-to-chip connection

Patent metadata

Field	Value
Publication number	US-2016013153-A1
Application number	US-201414329717-A
Country	US
Kind code	A1
Filing date	Jul 11, 2014
Priority date	Jul 11, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

An apparatus includes at least a first IC die and a second IC die. Bottom surfaces of the first and second IC dice include a first plurality of connection pads and top surfaces of the first and second IC dice include a second plurality of connection pads. The apparatus also includes a layer of non-conductive material covering the top surfaces of the first and second IC dice, a plurality of through-vias, first conductive interconnect between at least a portion of the first plurality of connection pads and at least one through via, and second conductive interconnect on a top surface of the layer of non-conductive material that provides electrical continuity between at least a portion of the second plurality of connection pads and at least one through-via of the plurality of through-vias.

First claim

What is claimed is:

1 . An apparatus comprising:
at least a first integrated circuit (IC) die and a second IC die, wherein bottom surfaces of the first and second IC dice include a first plurality of connection pads and top surfaces of the first and second IC dice include a second plurality of connection pads; a layer of non-conductive material covering the top surfaces of the first and second IC dice; a plurality of through-vias including at least one through-via in the first IC die and at least one through-via in the second IC die; first conductive interconnect between at least a portion of the first plurality of connection pads and at least one through via of the plurality of through vias; and second conductive interconnect on a top surface of the layer of non-conductive material that provides electrical continuity between at least a portion of the second plurality of connection pads and at least one through-via of the plurality of through-vias.

2 . The apparatus of claim 1 , wherein at least one through-via of the plurality of through-vias is included in the layer of non-conductive material and extends to the top surface of the layer of non-conductive material, and the second conductive interconnect provides electrical continuity to the at least one through-via included in the layer of non-conductive material.

3 . The apparatus of claim 1 , wherein the layer of non-conductive material includes a molded layer of laminate material over the first and second IC dice.

4 . The apparatus of claim 1 , wherein the layer of non-conductive material includes a molded layer of reconstituted wafer over the first and second IC dice.

5 . The apparatus of claim 4 , including a redistribution layer on at least one of the top surface and bottom surface of the first and second IC dice, wherein at least one of a portion of the first conductive interconnect or a portion of the second conductive interconnect is included in the redistribution layer.

6 . The apparatus of claim 1 , including one or more landing pads on a bottom side of the IC dice and at least one through-via of the plurality of through-vias provides electrical continuity between at least one landing pad and the second conductive interconnect.

7 . The apparatus of claim 1 , wherein the second conductive interconnect includes a bridge component arranged on the top surfaces of the first and second IC dice.

8 . The apparatus of claim 7 , including:
a substrate, wherein the first and second IC dice are arranged on the substrate; a first bond layer between the bottom surfaces of first and second IC dice and a first side of the substrate; a second bond layer between the bridge component and the top surfaces of the first and second IC dice; and a plurality of bond pads arranged on the second side of the substrate and solder bumps arranged on at least a portion of the bond pads.

9 . The apparatus of claim 7 , including one or more bonds pads on each of the bottom surfaces of the first IC die and the second IC die and the first conductive interconnect provides electrical continuity between a bond pad of the first IC die and the at least one through-via of the first IC die and electrical continuity between a bond pad of the second IC die and the at least one through-via of the second IC die, and the second conductive interconnect provides electrical continuity between the at least one through-via of the first IC die and the at least one through-via of the second IC die.

10 . The apparatus of claim 1 , wherein the first IC die includes only digital circuits and the second IC die includes analog circuits.

11 . A method comprising:
forming a first integrated circuit (IC) die and a second IC die to include a first plurality of connection pads on a bottom surface of each of the first and second IC dice and a second plurality of connection pads on the top surface of each of the first and second IC dice; covering at least the top surfaces of the first and second IC dice with a layer of non-conductive material to form a subassembly; forming a plurality of through-vias in the subassembly; forming openings in the non-conductive material to at least a portion of the second plurality of connection pads; and forming first conductive interconnect between at least a portion of the first plurality of connection pads; and forming second conductive interconnect on a top surface of the layer of non-conductive material that provides electrical continuity between at least a portion of the second plurality of connection pads and at least one through-via of the plurality of through-vias.

12 . The method of claim 11 , wherein forming the at least one through-via includes forming at least one of a through silicon via (TSV) in one or both of the first and second IC dice or forming the through-via in the layer of non-conductive material.

13 . The method of claim 11 , wherein covering at least the top surfaces of the first and second IC dice includes molding a layer of laminate material over the first and second IC dice.

14 . The method of claim 11 , wherein covering at least the top surfaces of the first and second IC dice includes molding a layer of reconstituted wafer over the first and second IC dice.

15 . The method of claim 14 , including forming at least one of a portion of the first conductive interconnect or a portion of the second conductive interconnect in a redistribution layer and arranging the redistribution layer on at least one of a top side or a bottom side of the subassembly.

16 . The method of claim 11 , wherein forming electrical interconnection includes arranging a bridge component on the top surfaces of the first and second IC dice prior to covering the top surfaces of the first and second IC dice with the non-conductive material, wherein the bridge component includes at least a portion of the second conductive interconnect.

17 . The method of claim 16 , including:
mounting the bottom surfaces of the first and second IC dice to a first side of a substrate using a first bond layer, wherein the first bond layer includes at least one of solder bumps or copper pillars; and arranging a second bond layer on a second side of the substrate, wherein the second layer includes solder bumps, and wherein the substrate includes third conductive interconnect to provide electrical continuity between at least a portion of the first bond layer and the second bond layer.

18 . The method of claim 11 , wherein the first conductive interconnect includes providing electrical continuity between a connection pad on the bottom surface of the first IC die and at least one through-via of the plurality of through-vias and forming second conductive interconnect includes providing electrical continuity between the at least one through-via and a connection pad on the top surface of the second IC die.

19 . An apparatus comprising:
an IC die including a top surface and a bottom surface, wherein the bottom surface includes a first plurality of connection pads and the top surface includes a second plurality of connection pads; a layer of non-conductive material covering the top surface and substantially covering the side surfaces of the IC die; a plurality of through-vias; first conductive interconnect that provides electrical continuity to at least a portion of the first plurality of connection pads and at least one through-via of the plurality of through-vias; and second conductive interconnect on a top surface of the layer of non-conductive material that provides electrical continuity

Assignees

• Intel Ip Corp

Inventors

• Meyer Thorsten

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title