Low fabrication cost, high performance, high reliability chip scale package
US-9369175-B2 · Jun 14, 2016 · US
Damascene re-distribution layer (RDL) in fan out split die application
US9583462B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9583462-B2 |
| Application number | US-201514689011-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 16, 2015 |
| Priority date | Jan 22, 2015 |
| Publication date | Feb 28, 2017 |
| Grant date | Feb 28, 2017 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A semiconductor device may include a first semiconductor die. A passivation layer supports the first semiconductor die. The passivation layer may include a first via having a barrier layer and a first redistribution layer (RDL) conductive interconnect coupled to the first via through the barrier layer. The first via may couple the first semiconductor die to the first RDL conductive interconnect.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: a first semiconductor die; and a passivation layer supporting the first semiconductor die, the passivation layer comprising a first via having a first barrier layer and a first redistribution layer (RDL) conductive interconnect having a second barrier layer, wherein the first RDL conductive interconnect is coupled to the first via and the first barrier layer through the second barrier layer, the first via coupling the first semiconductor die to the first RDL conductive interconnect. 2. The semiconductor device of claim 1 , further comprising: a second semiconductor die; and a second via having the first barrier layer and coupled to the first RDL conductive interconnect having the second barrier layer through the second barrier layer, the second via coupling the second semiconductor die to the first RDL conductive interconnect. 3. The semiconductor device of claim 1 , further comprising: a second via coupled to the first RDL conductive interconnect through a third barrier layer; and a second RDL conductive interconnect directly coupled to the second via. 4. The semiconductor device of claim 3 , further comprising a package interconnect layer directly coupled to the second RDL conductive interconnect. 5. The semiconductor device of claim 1 , further comprising at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer. 6. A semiconductor device, comprising: a first semiconductor die; and a passivation layer supporting the first semiconductor die, the passivation layer comprising a first via having a first barrier layer, a second via having the first barrier layer and a means for interconnecting the first via, the first barrier layer, and the second via through a second barrier layer, the first via coupling the first semiconductor die to the interconnecting means. 7. The semiconductor device of claim 6 , further comprising a second semiconductor die coupled to the first interconnecting means by the second via. 8. The semiconductor device of claim 6 , further comprising: a package conductive interconnect; and means for directly interconnecting the package conductive interconnect and the second via. 9. The semiconductor device of claim 6 , further comprising additional vias and means for directly interconnecting the additional vias to each other but not through the second barrier layer. 10. The semiconductor device of claim 6 , the semiconductor device integrated into a circuit, the circuit incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.
Assignees
Inventors
Classifications
characterised by the relative positions of pads or connectors relative to package parts · CPC title
Configurations of laterally-adjacent chips · CPC title
the encapsulations exposing the passive side of the semiconductor body · CPC title
using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title
on encapsulations · CPC title
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9583462B2 cover?
- A semiconductor device may include a first semiconductor die. A passivation layer supports the first semiconductor die. The passivation layer may include a first via having a barrier layer and a first redistribution layer (RDL) conductive interconnect coupled to the first via through the barrier layer. The first via may couple the first semiconductor die to the first RDL conductive interconnect.
- Who is the assignee on this patent?
- Qualcomm Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W70/614. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).