Switching element, variable resistance memory device, and method of manufacturing the switching element

Patent metadata

Field	Value
Publication number	US-10777745-B2
Application number	US-201916364232-A
Country	US
Kind code	B2
Filing date	Mar 26, 2019
Priority date	Sep 4, 2018
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

A switching element includes a lower barrier electrode on a substrate, a switching pattern on the lower barrier electrode, and an upper barrier electrode on the switching pattern. The lower barrier electrode includes a first lower barrier electrode layer, and a second lower barrier electrode layer interposed between the first lower barrier electrode layer and the switching pattern and whose density is different from the density of the first lower barrier electrode.

First claim

What is claimed is:

1. A switching element comprising:
a lower barrier electrode on a substrate;
a switching pattern on the lower barrier electrode; and
an upper barrier electrode on the switching pattern,
wherein the lower barrier electrode comprises:
a first lower barrier electrode layer; and
a second lower barrier electrode layer interposed between the first lower barrier electrode layer and the switching pattern, the second lower barrier electrode layer having a density different from that of the first lower barrier electrode layer,
wherein the first lower barrier layer includes carbon and the second lower barrier layer includes carbon.

2. The switching element of claim 1 , wherein the density of the second lower barrier electrode layer is higher than the density of the first lower barrier electrode layer.

3. The switching element of claim 2 , wherein the density of the first lower barrier electrode layer is about 1.7 g/cm 3 , and the density of the second lower barrier electrode layer is about 2.3 g/cm 3 .

4. The switching element of claim 1 , wherein resistivity of the second lower barrier electrode layer is less than that of the first lower barrier electrode layer.

5. The switching element of claim 1 , wherein surface roughness of the second lower barrier electrode layer is less than that of the first lower barrier electrode layer.

6. The switching element of claim 1 , wherein the upper barrier electrode comprises:
a first upper barrier electrode layer; and
a second upper barrier electrode layer which is disposed on the first upper barrier electrode layer and has a density different from that of the first upper barrier electrode layer.

7. The switching element of claim 6 , further comprising:
an upper electrode on the upper barrier electrode,
wherein the density of the second upper barrier electrode layer is lower than that of the first upper barrier electrode layer.

8. The switching element of claim 6 , wherein the density of the second upper barrier electrode layer is higher than the density of the first upper barrier electrode layer.

9. The switching element of claim 1 , wherein the switching pattern includes a chalcogenide element.

10. A variable resistance memory device comprising:
a first conductive line extending longitudinally in a first direction;
a second conductive line extending longitudinally in a second direction intersecting the first direction when the first conductive line and the second conductive line are viewed in a plan view;
a variable resistance structure interposed between the first and second conductive lines; and
a switching element interposed between the variable resistance structure and the second conductive line,
wherein the switching element comprises:
a lower barrier electrode;
a switching pattern on the lower barrier electrode; and
an upper barrier electrode on the switching pattern, and
wherein the lower barrier electrode comprises:
a first lower barrier electrode layer; and
a second lower barrier electrode layer interposed between the first lower barrier electrode layer and the switching pattern, the second lower barrier electrode layer having a density different from that of the first lower barrier electrode layer.

11. The variable resistance memory device of claim 10 , further comprising:
an intermediate electrode interposed between the first lower barrier electrode layer and the variable resistance structure.

12. The variable resistance memory device of claim 11 , wherein a width of the first lower barrier electrode layer is greater than a width of the intermediate electrode.

13. The variable resistance memory device of claim 10 , wherein the upper barrier electrode comprises:
a first upper barrier electrode layer; and
a second upper barrier electrode layer which is interposed between the first upper barrier electrode layer and the second conductive line and has a density different from that of the first upper barrier electrode layer.

14. The variable resistance memory device of claim 10 , wherein the switching element further comprises an upper electrode interposed between the upper barrier electrode and the second conductive line.

15. A variable resistance memory device comprising:
a first conductive line;
a second conductive line; and
a memory cell interposed between and electrically connected to the first and second conductive lines, the memory cell including a variable resistor whose resistivity is temperature dependent and a switch interposed between the variable resistor and the second conductive line,
wherein the switch comprises:
a switching pattern that selectively electrically conductively connects the variable resistor to the second conductive line,
a first lower layer of barrier material interposed between the variable resistor and the switching pattern, and
a second lower layer of barrier material interposed between the first lower layer of barrier material and the switching pattern, the barrier material of the second lower layer having a density different from that of the barrier material of the first lower layer.

16. The variable resistance memory device of claim 15 , wherein the density of the barrier material of the second lower layer of the switch is higher than the density of the barrier material of the first lower layer of the switch.

17. The variable resistance memory device of claim 16 , wherein the first lower layer of the switch is a carbon film and the second lower layer of the switch is a carbon film.

18. The variable resistance memory device of claim 15 , wherein the switching pattern is of a compound that includes a chalcogenide element.

19. The variable resistance memory device of claim 15 , wherein the variable resistor comprises a pattern of phase change material having a phase transition temperature across which a state of the phase change material changes between a crystalline state and an amorphous state, and further comprising:
a heating electrode interposed between the variable resistor and the first conductive line.

Assignees

• Samsung Electronics Co Ltd

Inventors

• YU Seung-Geun
• Wu Zhu
• Lee Ja Bin
• Lee Jung Moo
• Lee Jinwoo
• Jung Kyubong

Classifications

• H10N70/826 Primary

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10N70/882

  Compounds of sulfur, selenium or tellurium, e.g. chalcogenides · CPC title

• H10N70/841 Primary

  Electrodes · CPC title

• H10N70/026

  by physical vapor deposition, e.g. sputtering · CPC title

• H01L45/1666

  Electricity · mapped topic