Phase change memory cells including nitrogenated carbon materials, methods of forming the same, and phase change memory devices including nitrogenated carbon materials
US-9054295-B2 · Jun 9, 2015 · US
Electrode materials and interface layers to minimize chalcogenide interface resistance
US9543515B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9543515-B2 |
| Application number | US-201314073927-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 7, 2013 |
| Priority date | Nov 7, 2013 |
| Publication date | Jan 10, 2017 |
| Grant date | Jan 10, 2017 |
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Abstract
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A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof. In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm.
First claim
Opening claim text (preview).
The invention claimed is: 1. A phase-change memory cell, comprising: a chalcogenide-based phase-change memory layer; a first electrode layer; a first interface layer between the chalcogenide-based phase-change memory layer and the first electrode layer and in contact with each of the chalcogenide-based phase-change memory layer and the first electrode layer, the first interface layer comprising a boride to provide a reduced resistance between the chalcogenide-based phase-change memory layer and the first electrode layer; a second interface layer between the chalcogenide-based phase-change memory layer and the second electrode layer and in contact with each of the chalcogenide-based phase-change memory layer and the second electrode layer, the second interface layer comprising a boride to provide a reduced resistance between the chalcogenide-based phase-change memory layer and the second electrode layer; a switching device layer comprising an ovonic threshold switch; a third electrode layer; a third interface layer between the switching device layer and the second electrode layer and in contact with each of the switching device layer and the second electrode layer; and a fourth interface layer between the switching device and the third electrode layer and in contact with each of the switching device layer and the third electrode layer. 2. The phase-change memory cell according to claim 1 , the first interface layer comprises a tungsten boride, or a molybdenum boride, or a combination thereof. 3. The phase-change memory cell according to claim 1 , wherein the first interface layer comprises a thickness of between about 1 nm and about 10 nm. 4. The phase-change memory cell according to claim 1 , wherein the second interface layer comprises a tungsten boride, or a molybdenum boride, or a combination thereof. 5. The phase-change memory cell according to claim 1 , wherein the second interface layer comprises a thickness of between about 1 nm and about 10 nm. 6. The phase-change memory cell according to claim 1 , wherein the third interface layer comprises a tungsten boride, or a molybdenum boride, or a combination thereof, and wherein the fourth interface layer comprises a tungsten boride, or a molybdenum boride, or a combination thereof. 7. The phase-change memory cell according to claim 1 , wherein the chalcogenide-based phase-change memory layer comprises Ge2Sb2Te5 or In3SbTe2.
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9543515B2 cover?
- A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the …
- Who is the assignee on this patent?
- Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification H01L45/16. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 10 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).