Electronic device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9722172-B2
Application number	US-201514789798-A
Country	US
Kind code	B2
Filing date	Jul 1, 2015
Priority date	Nov 24, 2014
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes an interlayer dielectric layer formed over a substrate and having a hole; a conductive pattern filled in the hole and having a top surface located at a level substantially same as a top surface of the interlayer dielectric layer; and an MTJ (Magnetic Tunnel Junction) structure formed over the conductive pattern to be coupled to the conductive pattern and including a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein an upper portion of the conductive pattern includes a first amorphous region.

First claim

What is claimed is:

1. An electronic device comprising a semiconductor memory, wherein the semiconductor memory includes:
an interlayer dielectric layer formed over a substrate and having a hole;
a conductive pattern filled in the hole and having a top surface located at a level substantially same as a top surface of the interlayer dielectric layer; and
an MTJ (Magnetic Tunnel Junction) structure formed over the conductive pattern to be coupled to the conductive pattern and including a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer,
wherein an upper portion of the conductive pattern includes a first amorphous region.

2. The electronic device of claim 1 , wherein the first amorphous region includes Ge, Ar, Xe, In, Sb or As as a dopant.

3. The electronic device of claim 1 , wherein an upper portion of the interlayer dielectric layer includes a second amorphous region.

4. The electronic device of claim 3 , wherein the second amorphous region includes Ge, Ar, Xe, In, Sb or As as a dopant.

5. The electronic device of claim 3 , wherein the upper portion of the conductive pattern and the upper portion of the interlayer dielectric layer have the same dopant.

6. The electronic device of claim 3 , wherein the upper portion of the conductive pattern and the upper portion of the interlayer dielectric layer have the substantially same thickness.

7. The electronic device of claim 1 , wherein the MTJ structure covers the whole top surface of the conductive pattern.

8. The electronic device of claim 1 , wherein the conductive pattern includes a first conductive pattern filling a lower portion of the hole and a second conductive pattern filling an upper portion of the hole, and
the second conductive pattern forms a variable resistance element together with the MTJ structure.

9. The electronic device of claim 8 , wherein the upper portion of the conductive pattern corresponds to a part or a whole of the second conductive pattern.

10. The electronic device of claim 8 , wherein the hole includes a first hole and a second hole located over the first hole,
the second hole has a sidewall which is not aligned with the first hole,
the first conductive pattern is filled in the first hole, and
the second conductive pattern is filled in the second hole.

11. The electronic device according to claim 1 , further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;
an operation unit configured to perform an operation based on a result that the control unit decodes the command; and
a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,
wherein the semiconductor memory is part of the memory unit in the microprocessor.

12. The electronic device according to claim 1 , further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;
a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and
a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,
wherein the semiconductor memory is part of the cache memory unit in the processor.

13. The electronic device according to claim 1 , further comprising a processing system which includes:
a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;
an auxiliary memory device configured to store a program for decoding the command and the information;
a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and
an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside,
wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.

14. The electronic device according to claim 1 , further comprising a data storage system which includes:
a storage device configured to store data and conserve stored data regardless of power supply;
a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside;
a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and
an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside,
wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system.

15. The electronic device according to claim 1 , further comprising a memory system which includes:
a memory configured to store data and conserve stored data regardless of power supply;
a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside;
a buffer memory configured to buffer data exchanged between the memory and the outside; and
an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside,
wherein the semiconductor memory is part of the memory or the buffer memory in the memory system.

16. A method for fabricating an electronic device comprising a semiconductor memory, comprising:
forming an interlayer dielectric layer having a hole over a substrate;
forming a conductive pattern filled in the hole;
amorphizing an upper portion of the conductive pattern by performing an ion implantation process so that the conductive pattern and the interlayer dielectric layer have a substantially flat top surface; and
forming an MTJ (Magnetic Tunnel Junction) structure over the substantially flat top surface, the MTJ structure being coupled to the conductive pattern and including a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer.

17. The method of claim 16 , wherein the ion implantation process is performed in a state where a protective layer is formed over the conductive pattern and the interlayer dielectric layer.

18. The method of claim 17 , wherein the protective layer is removed after the ion implantation process.

19. The method of claim 16 , wherein the ion implantation process is performed on whole top surfaces of the conductive pattern and the interlayer dielectric layer.

20. The method of claim 16 , wherein at least one dopant of Ge, Ar, Xe, In, Sb or As is implanted in the ion implantation process.

Assignees

• Sk Hynix Inc

Inventors

• Park Ki-Seon
• Lee Bo-Mi
• Choi Won-Joon
• Kim Guk-Cheon

Classifications

• H01L43/08 Primary

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• H10N50/01

  Manufacture or treatment · CPC title